Table 3-1. Control Register 4 (Cr4) Fields - AMD K5 Technical Reference Manual

18524C/0—Nov1996

Table 3-1. Control Register 4 (CR4) Fields

Bit Mnemonic
7 GPE
6 MCE
4 PSE
3 DE
2 TSD
1 PVI
0 VME
Control Register 4 (CR4) Extensions
Description
Global Page
Extension
Machine-Check Enable
Page Size
Extension
Debugging
Extensions
Time Stamp
Disable
Protected Virtual
Interrupts
Virtual-8086
Mode Extensions
AMD-K5 Processor Technical Reference Manual
Function
Enables retention of designated entries in the 4-Kbyte TLB or
4-Mbyte TLB during invalidations.
1 = enabled, 0 = disabled.
See Section 3.1.3 on page 3-9 for details.
Enables machine-check exceptions.
1 = enabled, 0 = disabled.
See Section 3.1.1 on page 3-4 for details.
Enables 4-Mbyte pages.
1 = enabled, 0 = disabled.
See Section 3.1.2 on page 3-5 for details.
Enables I/O breakpoints in the DR7–DR0 registers.
1 = enabled, 0 = disabled.
See Section 7.5 on page 7-16 for details.
Selects privileged (CPL=0) or non-privileged (CPL>0) use of
the RDTSC instruction, which reads the Time Stamp Counter
(TSC).
1 = CPL must be 0, 0 =any CPL.
See Section 3.2.3 on page 3-27 for details.
Enables hardware support for interrupt virtualization in Pro-
tected mode.
1 = enabled, 0 = disabled.
See Section 3.1.5 on page 3-24 for details.
Enables hardware support for interrupt virtualization in Vir-
tual-8086 mode.
1 = enabled, 0 = disabled.
See Section 3.1.4 on page 3-12 for details.
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