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Rev
October
Revision Guide for AMD Family
h Models
h- Fh Processors
Scrub Rate Control Register Address Depends on DctCfgSel
Description
When DCT Configuration Select DctCfgSel D F x C
is b accesses to the Scrub Rate Control register
D F x
incorrectly accesses a different register that does not actually affect any hardware
Potential Effect on System
Incorrect scrub rate controls may be read or in effect
Suggested Workaround
Software should clear DctCfgSel D F x C
to b prior to any access to D F x
Scrub Rate Control
Register The software must serialize any accesses to D F x
with other accesses to registers that use
DctCfgSel
When enabling scrub settings BIOS should write D F x
twice with the same value - once with
D F x C
set to b and once with D F x C
set to b
BIOS should program D F x C
to b before handing over control to the operating system
Fix Planned
No fix planned
Product Errata
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