Table 2-2. Cache States For Read And Write Accesses - AMD K5 Technical Reference Manual

18524C/0—Nov1996

Table 2-2. Cache States for Read and Write Accesses

Type
Read Miss
Cache Read
Read
Hit
Write Miss
Cache
Write
Write Hit
Notes:
1. Linear tags are masked by A20M, physical tags are not.
2. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32 bytes.
3. If CACHE and KEN are Low.
4. If PWT is Low and WB/WT is High.
5. MESI state is stored in the physical tags. Instruction-cache state consists only of valid (shared) or invalid, and there are no write-
related states.
— Not applicable or none.
Cache Organization and Management
1 Cache State
Tags
Before Access
invalid
Linear
3
invalid (cache-
able)
shared
Linear exclusive
modified
Linear invalid
shared
Linear
exclusive or
modified
AMD-K5 Processor Technical Reference Manual
Access
5 2
Type
MESI State
single read
burst read (line
fill)
—
—
—
single write
cache update
and single write
cache update
Cache State After Access
5 Writeback-
Writethrough
State
invalid invalid
shared or writethrough or
4
exclusive writeback
shared writethrough
exclusive writeback
modified writeback
invalid invalid
shared or writethrough or
4
exclusive writeback
modified writeback
4
4
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