Operating Mode And Default Register Values - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
6.3.1

Operating Mode and Default Register Values

6-24
The software environment in SMM has the following features:
Addressing as in Real mode
4-Gbyte segment limit
Default 16-bit operand, address, and stack size, although
instruction prefixes can override these defaults
Control transfers that do not override the default operand
size truncate the EIP to 16 bits
Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in Real mode
segment-base addressing.
A20M is not recognized (unlike the Pentium processor)
Interrupt vectors use the Real-mode interrupt vector table
(but see Section 6.3.8 on page 6-32)
The IF flag in EFLAGS is cleared (INTR not recognized)
The NMI interrupt is disabled
The TF flag in EFLAGS is cleared (single-step traces dis-
abled)
Debug register DR7 is cleared (debug traps disabled)
Figure 6-2 on page 6-7 shows the default map of the SMM mem-
ory area. It consists of a 64-Kbyte area, between 0003_0000h
and 0003_FFFFh, of which the top 32-Kbytes (0003_8000h and
0003_FFFFh) must be populated with RAM. The default code-
segment (CS) base address for the area—called the SMM Base
Address—is at 0003_0000h. The top 512 bytes (0003_FFFFh to
0003_FE00h) contain a fill-down SMM state-save area. The
default entry point for the SMM service routine is at
0003_8000h.
Table 6-1 shows the initial state of registers when entering
SMM.
18524C/0—Nov1996
System Design