A.5 Power Saving Features; A.5.1 Stpclk In Halt State; One Instruction Executes; A.5.3 Simultaneous I/O Smi Trap And Debug Breakpoint Trap - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
A.5 Power Saving Features
A.5.1 STPCLK in Halt State
A.5.2 STPCLK Pulse does not Guarantee That One Instruction
Executes
A.5.3 Simultaneous I/O SMI Trap and Debug Breakpoint Trap
A-12
When in the Halt state, the AMD-K5 processor responds to
STPCLK and enters the Stop Grant state. The Pentium proces-
sor ignores STPCLK in the Halt state.
Unlike the Pentium processor, the AMD-K5 processor does not
guarantee that at least one instruction will be executed
between the negation of STPCLK and a subsequent reassertion
of STPCLK. On the Pentium processor, at least one instruction
is guaranteed to execute.
On a simultaneous I/O SMI trap and debug breakpoint trap, the
AMD-K5 processor responds to the SMI first and postpones
writing the fault frame for the debug trap to the stack until
after the resumption of normal execution via RSM. (If debug
registers DR3–DR0 are going to be used while in SMM, they
must be saved and restored by the SMM software. DR6 and
DR7 are automatically saved and restored.) This is similar to
the Pentium processor behavior (P54C only) with TR12.ITR set
to 1, although the postponing of the debug trap is only accom-
plished with trapped I/O instructions, where the timing of the
SMI met the requirements for SMI I/O trapping.
On the AMD-K5 processor, if, on the RSM, the I/O Restart Flag
in the SMM save area is set, the debug trap is cancelled and
will be redetected as a result of the reexecution of the I/O
instruction.
18524C/0—Nov1996