Table 7-6. Public Tap Instructions - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
7.8.2 Public Instructions

Table 7-6. Public TAP Instructions

Instruction Encoding
EXTEST
SAMPLE/
PRELOAD
IDCODE
HIGHZ
ALL1
ALL0
USEHDT
RUNBIST
BYPASS
BYPASS undefined
Notes:
1. Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement.
7-22
The processor supports all three IEEE-mandatory instructions
(BYPASS, SAMPLE/PRELOAD, EXTEST), three IEEE-
optional instructions (IDCODE, HIGHZ, RUNBIST), and three
instructions unique to the AMD-K5 processor (ALL1, ALL0,
USEHDT). Table 7-6 shows the complete set of public TAP
instructions supported by the processor. In addition, the pro-
cessor implements several private manufacturing test instruc-
tions.
The IEEE standard describes the mandatory and optional
instructions. The ALL1 and ALL0 instructions simply force all
outputs and bidirectionals High or Low. The USEHDT instruc-
tion is described below. Any instruction encodings not shown
in Table 7-6 select the BYPASS instruction.
Register
00000 BSR
00001 BSR
00010 DIR
00011 BR
00100 BR
00101 BR
00110 HDTR
00111 BISTRR
11111 BR
BR
Description
As defined by the IEEE standard
As defined by the IEEE standard
As defined by the IEEE standard
As defined by the IEEE standard
Forces all outputs and bidirectionals High
Forces all outputs and bidirectionals Low
Accesses the Hardware Debug Tool (HDT)
See Section 7.9 on page 7-23
As defined by the IEEE standard
As defined by the IEEE standard
Undefined instruction encodings select the BYPASS
instruction
18524C/0—Nov1996
1
Test and Debug