Burst Cycles; Burst Read - AMD K5 Technical Reference Manual

18524C/0—Nov1996
5.4.3

Burst Cycles

Burst Read

Bus Cycle Timing
The processor drives burst cycles, which consist of four sequen-
tial eight-byte (quadword) transfers on the data bus, only in
the following cases:
Burst Read—Cache-line fills from memory. These burst
reads occur when the processor asserts CACHE during ADS
and system logic asserts KEN during the first BRDY of a
read cycle.
Burst Write—Writebacks to memory of modified cache lines.
Writebacks can be caused by (a) externally initiated
inquire cycles or FLUSH operations, (b) processor-initiated
internal snoops or cache-line replacements, or (c) program-
initiated WBINVD instructions.
Writethroughs to memory, which occur in response to write
misses or write hits to shared cache lines, are driven as single-
transfer bus cycles.
Figure 5-6 shows two consecutive burst reads. During burst
reads (CACHE and KEN both asserted with the first BRDY of a
memory read), the processor drives BE7–BE0 with ADS to
identify the bytes of the desired instruction or operand. The
processor drives BE7–BE0 with the desired bytes at that time
because it does not yet know whether the read will be a single-
transfer or a burst—this depends on how system logic drives
KEN with the first BRDY. If system logic negates KEN it must
return, as a single transfer, only the bytes specified on BE7–
BE0. If system logic asserts KEN, it must ignore BE7–BE0 dur-
ing all transfers of the burst and return all eight bytes for the
starting address on A31–A3. BE7–BE0 does not change during
the four transfers of the burst. (This behavior is unlike the 486
processor, which drives BE3–BE0 separately for each transfer
of a burst.) System logic must determine the successive quad-
word addresses for each transfer in a burst, depending on the
starting address, as shown in Table 5-21.
AMD-K5 Processor Technical Reference Manual
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