Retire - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
2.2.5

Retire

2-12
The processor implements a real-state (non-speculative) regis-
ter file that contains the x86-architecture registers and a real-
state 8-Kbyte data cache. While ROPs complete out of order
and their results are forwarded to other execution units and to
the ROB out of order, their results are always written at retire-
ment time to the real-state x86 registers in program order.
Likewise, as results are written from the load/store units to the
store buffer out of order, they are always written at retirement
time to the data cache and/or memory in program order.
An x86 instruction is said to retire when the ROB or store
buffer writes the operands for all of its ROPs, in program
order, to the x86 real-state registers or the data cache. At the
point of retirement, the register file and data cache fully
reflect the execution of an instruction. Any associated excep-
tions are recognized (the ROB facilitates precise exception
handling), any external interrupts that were latched or are cur-
rently held asserted are recognized, and the instruction
pointer is updated. For instructions that store an operand to
memory, retirement is the time at which the store is guaran-
teed to be written externally. When a pipeline invalidation
(flush) occurs, it does so at the retirement stage, causing all
instructions in the pipeline that have not reached the retire-
ment stage to be invalidated.
The retirement stage is also called the instruction-retirement
boundary, or simply instruction boundary. The processor can
retire up to four instructions per processor clock. Thus, the
next set of up to four instructions that are candidates to retire
determines the next instruction boundary at which an external
interrupt can be recognized.
Only one store from the store buffer can be among the set of up
to four instructions that retire simultaneously. If the set of
retirement candidates in any clock includes more than one
store, only those instructions up to (but not including) the sec-
ond store will retire. The remaining stores occur one at a time,
in their queued order, during subsequent retire cycles.
18524C/0—Nov1996
Internal Architecture