Figure 6-6. Clock Control State Transitions - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
Halt
State

Figure 6-6. Clock Control State Transitions

6-36
HLT Instruction
Normal Mode
- Real
RESET, SMI, INIT,
- Virtual-8086
or INTR Asserted
- Protected
- SMM
STPCLK Asserted
STPCLK Negated
EADS
Stop Grant
Inquire
State
STPCLK Asserted
STPCLK Negated,
or RESET Asserted
EADS
Stop Grant
State
CLK
Started
Stop Clock
State
18524C/0—Nov1996
CLK
Stopped
System Design