Table 5-17. Mesi-State Transitions For Reads - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual

Table 5-17. MESI-State Transitions for Reads

Signal or Event
1
CACHE, PCD
KEN
PWT
WB/WT
Cache-Line Fill
(32 bytes)
2
State After Read
Notes:
— Don't care or not applicable.
1. The PCD bit is one determinant of the state of CACHE.
2. Transition occurs after any line fill. Lines in shared MESI state are said to be in writethrough state. Those in exclusive or modified
MESI states are said to be in writeback state.
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the exclusive state, a subsequent write hit to the same line tran-
sitions the line to the modified state. During write hits, the
states of PWT and WB/WT can only change a line from shared
to exclusive; it cannot change an exclusive line to a shared line.
Read Miss
1 — 0
— 1 0
— — 1
— — —
no no yes
— — shared
Result of Cache Lookup
0 0
0 0
— 0
0 1
yes yes
shared exclusive
18524C/0—Nov1996
Read Hit
shared exclusive
— —
— —
— —
— —
no no
shared exclusive
Bus Interface
modified
—
—
—
—
no
modified