Table 5-12. Outputs Floated When Hlda Is Asserted; Hlda (Bus-Hold Acknowledge) - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
5.2.27

HLDA (Bus-Hold Acknowledge)

Summary
Driven
Details
5-74
Output
When system logic asserts HOLD, the processor completes any
in-progress bus cycle, floats its cycle-driving outputs, and
asserts HLDA as an acknowledgment. While HLDA is asserted,
another bus master can drive cycles on the bus, including
inquire cycles to the processor.
The processor drives HLDA every clock. The processor floats
the cycle-driving outputs on the bus and asserts HLDA two
clocks after the last BRDY of an in-progress bus cycle, if such a
cycle is in progress when HOLD is asserted, or two clocks after
the assertion of HOLD, whichever comes last. The processor
continues to float the bus and assert HLDA until two clocks
after HOLD is negated.
HLDA is driven during cache hits in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM, but
writebacks wait until HLDA is negated. HLDA is also driven in
the Shutdown, Halt, Stop Grant, and Stop Clock states; or
while AHOLD, BOFF, RESET, INIT, or PRDY is asserted.
HLDA is not driven during processor-originated bus cycles,
because any such pending bus cycle completes before the pro-
cessor asserts HLDA.
HLDA is the processor's acknowledgment to HOLD. HLDA
indicates that any in-progress bus cycle has completed and that
the output and bidirectional signals used for memory or I/O
accesses are floating. Table 5-12 shows the signals floated. The
same set of signals is floated with BOFF.

Table 5-12. Outputs Floated When HLDA is Asserted

Address and Cycle Definition
Address Parity
A31–A3
ADS
ADSC
AP
N/A
Data and
and Control Data Parity
D/C D63–D0
LOCK DP7–DP0
M/IO BE7–BE0
SCYC
W/R
18524C/0—Nov1996
Cache
Control
CACHE
PCD
PWT
N/A N/A
N/A N/A
Bus Interface