Table 5-22. Interrupt Acknowledge Operation Definition - AMD K5 Technical Reference Manual

18524C/0—Nov1996
Interrupt
Acknowledge
Operation
Bus Cycle Timing
Figure 5-19A shows system logic asserting INTR during a burst
read. The figure shows the resulting bus behavior, up to the
start of the interrupt handler. When the processor recognizes
an INTR interrupt at the next instruction-retirement bound-
ary, the processor performs the following actions:
Finish In-Progress Bus Cycle—In Figure 5-19A, a burst read is
in progress when system logic asserts INTR. The processor
supports only one such in-progress bus cycle.
Flush Instruction Pipeline—This is not visible on the bus.
Acknowledge Interrupt—The interrupt acknowledge opera-
tion consists of a locked pair of reads, as shown in Table
5-22. The first read is not functional (a protocol relic). The
second read returns the interrupt vector in D7–D0. (The
interrupt vector is an offset into an interrupt table.) System
logic must return a BRDY in response to both cycles. The
processor inserts at least one idle clock between the locked
reads.
System logic will typically not be able to determine the
instruction boundary on which the processor recognizes
INTR. Thus, as a practical matter, system logic should hold
INTR asserted until the beginning of the interrupt acknowl-
edge operation, or until there is some other evidence that
the interrupt service routine has been entered (for exam-
ple, the access to the interrupt-table address).

Table 5-22. Interrupt Acknowledge Operation Definition

Processor Outputs First Bus Cycle
D/C
M/IO
W/R
BE7–BE0
A31–A3
D63–D0
Disable Maskable Interrupts—The processor does this under
certain conditions (see Section 5.2.32 on page 5-84 for
details), and it is not visible on the bus.
As shown in Figure 5-19B and Figure 5-19C, following the inter-
rupt acknowledge operation and a quiet period during which
AMD-K5 Processor Technical Reference Manual
0
0
0
EFh
0
Interrupt vector expected from interrupt
(ignored)
Second Bus Cycle
0
0
0
FEh (low byte enabled)
0
controller on D7–D0
5-175