Cache Tags - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
2.3.3

Cache Tags

2-16
buffer, which resides between the load/store units and the data
cache, moves to the real-state data cache or memory.
Details on the data-cache storage formats and testing are given
in Section 7.4 on page 7-7.
The processor's caches are dual-tagged. That is, the processor
maintains two sets of tags—linear and physical—for each line
in the two caches. The linear tags are stored in the instruction
and data caches. The physical tags are stored in the memory
management unit (MMU), where the TLB is also located. The
physical-tag directories for each cache have one port.
Linear tags are read for all accesses to the instruction and data
caches. All read misses, memory writes, and snooping—both
external inquire cycles and automatic internal snooping—go
through the physical tags. The MESI cache-coherency state is
recorded in the physical tags.
Accesses to the data-cache physical tags add two clocks to the
one-clock linear-tag access. Accesses to the instruction-cache
physical tags add three clocks to the one-clock linear-tag
access. Thus, physical-tag accesses take a total of three clocks
for the data cache or four clocks for the instruction cache, but
they occur infrequently. For write hits to the data cache, how-
ever, the additional latency for accessing the physical tags
(needed to determine the MESI state) is transparent to pro-
gram execution because write hits are pipelined and can occur
at a sustained rate of one per clock.
There is a corresponding physical tag for each linear tag. Two
or more linear addresses can be aliased to a single physical
address. When the processor detects an aliased access to the
store buffer, the TLB and physical tags forward the access
directly from the store buffer without depending on a linear-
tag match in the data cache.
The linear tags for both caches are invalidated whenever pag-
ing is turned on or off, or when CR3 (the page-directory base
register) is loaded, except that during x86-architecture task
switches, the linear tags are only invalidated if the current and
new value for CR3 are different. When linear tags are invali-
18524C/0—Nov1996
Internal Architecture