Signal Characteristics - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
5.1.1

Signal Characteristics

Table 5-1. Summary of Signal Characteristics
Signal Type
1
I
A20M
A31–A3 I/O
ADS O
ADSC O
AHOLD I
AP I/O
APCHK O
BE7–BE0 O
BF (BF1–BF0) I
BOFF I
BRDY I
BRDYC I
BREQ O
BUSCHK I
CACHE O
CLK I
Notes:
1. Can be driven asynchronously or synchronously.
2. The term clock means bus clock (CLK). "+n" means n CLKs later.
3. "+n" means n CLKs after the named signal is sampled active. All outputs and bidirectionals are floated during the float test (FLUSH
at RESET).
5-4
Sampled (Input) or
Asserted (Output)
Every clock.
Output: From ADS until last expected BRDY of the bus
cycle.
Input: Same clock as EADS. A4–A3 are disabled for input.
First clock of bus cycle.
First clock of bus cycle.
Every clock.
(same as A31–A3)
Two clocks after EADS, for one clock.
From ADS until the last expected BRDY of the bus cycle.
Falling edge of RESET.
Every clock.
Every clock, from one clock after ADS until the last
expected BRDY of the bus cycle.
(same as BRDY)
First clock of every bus cycle (same as ADS), cache store,
cache-tag recovery, and aliased cache load. Asserted con-
tinuously while processor is held off bus and needs
access to continue.
Every BRDY. Recognized at the next instruction boundary.
From ADS until the last expected BRDY of the bus cycle.
Driven for all reads; only driven for writes during write-
backs.
Always.
Internal
2 Resistor
pullup
pullup
pullup
18524C/0—Nov1996
3
Floated
AHOLD +1,
BOFF +1 or
HLDA
BOFF +1 or
HLDA
BOFF +1 or
HLDA
AHOLD +1,
BOFF +1 or
HLDA
BOFF +1 or
HLDA
BOFF +1 or
HLDA
Bus Interface