Figure 5-24B. Cache-Writeback And Invalidation Cycle - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
KEN
LOCK
M/IO
W/R
CLK
Figure 5-24B. Cache-Writeback and Invalidation Cycle (WBINVD Instruction) Part 2
5-186
Cache Writeback and
invalidation special cycle
Cache invalidation
special cycle
18524C/0—Nov1996
Bus Interface