Tlb Miss (4-Kbyte Page) - AMD K5 Technical Reference Manual

18524C/0—Nov1996
TLB Miss
(4-Kbyte Page)
Bus Cycle Timing
Figure 5-17 shows a TLB miss for a 4-Kbyte page. An overview
of the 4-Kbyte paging mechanism is illustrated in Figure 3-2 on
page 3-5. The paging mechanism for 4-Mbyte pages (Figure 3-3
on page 3-6) is similar but somewhat simpler. The processor
has separate TLBs for the two page sizes.
If an address for an access cannot be found in the processor's
linearly addressed instruction or data cache, the TLB (which
helps translate linear addresses to physical addresses) is
searched for the entry associated with the accessed page. A
TLB miss occurs if the entry cannot be found. For accesses to a
4-Kbyte page that miss the TLB, the processor accesses first
the page-directory entry (PDE) in memory and then the page-
table entry (PTE) in memory to check, and if necessary set,
their Accessed (A) bits. During a write access (not shown in
this example), the processor also checks and, if necessary, sets
the PTE Dirty (D) bit.
The general sequence, both for PDE and PTE, is as follows for
accesses to a 4-Kbyte page:
The processor drives an unlocked read of the PDE or PTE to
see if the relevant bit (A or D) is set.
If the bit is cleared (0), the processor then drives a locked
read-modify-write (four-byte read followed by four-byte
write) to set the bit.
The example in Figure 5-17 shows the following specific
sequence:
Read The PDE—The A bit in the PDE is set, so nothing fur-
ther is done with the PDE.
Read The PTE—The A bit in the PTE is cleared, indicating
that the page has not been previously accessed since the
operating system last cleared the bit
Set The Accessed Bit—The processor performs a locked read-
write pair of bus cycles to set the A bit. The diagram shows
these cycles as a 4-byte PTE read followed by a 4-byte PTE
write. It asserts LOCK with the ADS of the read cycle and
holds it asserted until the BRDY of the write cycle.
Read The Desired Location (Cache-Line Fill)—The processor
reads the location that caused the TLB miss, filling a cache
line as a result of the access.
AMD-K5 Processor Technical Reference Manual
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