Figure 3-3. 4-Mbyte Paging Mechanism - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
CR3
31
Page Directory
Offset

Figure 3-3. 4-Mbyte Paging Mechanism

3-6
4-Mbyte
Page
Directory
PDE
22 21
Linear Address
To enable the 4-Mbyte paging option:
1. Set the Page Size Extension (PSE) bit in CR4 to 1.
2. Set the Page Size (PS) bit in the page-directory entry to 1.
3. Write the physical base addresses of 4-Mbyte pages in bits
31–22 of page-directory entries. (Bits 21–12 of these entries
must be cleared to 0 or the processor will generate a page
fault.)
4. Load CR3 with the base address of the page directory that
contains these page-directory entries.
4-Mbyte
Page
Byte
Page
Offset
Software Environment and Extensions
18524C/0—Nov1996
0