Table 7-3. Array Ids In Array Pointers; Array Pointer - AMD K5 Technical Reference Manual

18524C/0—Nov1996
7.4.2

Array Pointer

Cache and TLB Testing
The array pointers entered in EDX (Figures 7-3 through 7-8,
top) specify particular array locations. For example, in the
data- and instruction-cache arrays, the way (or column) and set
(or index) in the array pointer specifies a cache line in the 4-
way, set-associative array. The array pointers for data-cache
data and instruction-cache instructions further specify a dword
location within that cache line. In the data cache, this dword is
32 bits of data. In the instruction cache, this dword is two
instruction bytes plus their associated pre-decode bits. For the
4-Kbyte TLB, the way and set specify one of the 128 TLB
entries. For the 4-Mbyte TLB, one of only four entries is speci-
fied.
Bits 7–0 of every array pointer encode the array ID, which iden-
tifies the array to be accessed, as shown in Table 7-3. To sim-
plify multiple accesses to an array, the contents of EDX is
retained after the RDMSR instruction executes (EDX is nor-
mally cleared after a RDMSR instruction).

Table 7-3. Array IDs in Array Pointers

Array Pointer
Bits 7–0
E0h
E1h
ECh
E4h
E5h
EDh
E6h
E7h
E8h
E9h
EAh
EBh
AMD-K5 Processor Technical Reference Manual
Accessed Array
Data Cache: Data
Data Cache: Linear Tag
Data Cache: Physical Tag
Instruction Cache: Instructions
Instruction Cache: Linear Tag
Instruction Cache: Physical Tag
Instruction Cache: Valid Bits
Instruction Cache: Branch-Prediction Bits
4-Kbyte TLB: Page
4-Kbyte TLB: Linear Tag
4-Mbyte TLB: Page
4-Mbyte TLB: Linear Tag
7-9