Bus Cycle Overview; Table 5-19. Bus Cycle Definitions - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
5.3

Bus Cycle Overview

5.3.1 Cycle Definitions

Table 5-19. Bus Cycle Definitions

Type of Cycle
Single-Transfer Memory Read or
Write
Single-Transfer I/O Read or Write
Burst Memory Read or Write
Interrupt Acknowledge
Special
5-136
The bus signals described in the previous section combine to
form various types of bus transactions, or bus cycles. This sec-
tion summarizes the general features of the bus cycles: cycle
definition, addressing, alignment, and priorities. Section 5.4
describes the signal timing for specific types of bus cycles.
The processor begins driving a bus cycle when it asserts ADS.
Concurrent with ADS, it drives the set of signals indicated in
Table 5-19, which define the type of bus cycle. For memory
reads, memory writes, burst reads, and burst writes, D/C speci-
fies whether the bus cycle accesses code (instructions) or data.
M/IO specifies whether the cycle accesses memory or an I/O
port. W/R specifies whether the cycle is a read or write. The
assertion of CACHE indicates that the processor is writing or is
prepared to read a burst cycle consisting of four consecutive
transfers on the data bus. However, for a read, system logic
must confirm the burst by asserting KEN, or the bus cycle
becomes a single-transfer read. I/O accesses are always non-
burst cycles.
Signals
D/C M/IO
0 or 1 1
1 0
0 or 1 1
0 0
0 0
Interrupt acknowledge operations consist of a locked pair of
read cycles. Special bus cycles are further differentiated by
W/R CACHE
0 or 1 1
0 or 1 1
For reads, system logic must assert
0 or 1 0
KEN with BRDY.
0 — Pair of locked cycles.
Several special cycles distinguished by
1 — BE7–BE0 and A31–A3. See Table 5-23
on page 5-180.
18524C/0—Nov1996
Comments
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Bus Interface