Output-Float Test; Cache And Tlb Testing - AMD K5 Technical Reference Manual

18524C/0—Nov1996
7.3

Output-Float Test

7.4

Cache and TLB Testing

Output-Float Test
of the TAP BIST, the result remains in the BIST result register
for shifting out through the TDO signal. The TRST signal must
be asserted or the TAP instruction must be changed in order to
exit TAP BIST and return to normal operation.
The Output-Float Test mode is entered if FLUSH is asserted
before the falling edge of RESET. This causes the processor to
place all of its output and bidirectional signals in the high-
impedance state. In this isolated state, system board traces and
connections can be tested for integrity and driveability. The
Output-Float Test mode can only be exited by asserting RESET
again.
On the AMD-K5 and Pentium processors, FLUSH is an edge-
triggered interrupt. On the 486 processor, however, the signal
is a level-sensitive input.
Cache and TLB testing is often done by the BIOS or operating
system during power-up. These arrays can be tested using the
Array Access Register (AAR). The following tests can be per-
formed:
Data Cache—8-Kbyte, 4-way, set associative
Data array
•
Linear-tag array
•
Physical-tag array
•
Instruction Cache—16-Kbyte, 4-way, set associative
Instruction array
•
Linear-tag array
•
Physical-tag array
•
Valid-bit array
•
Branch-prediction bit array
•
AMD-K5 Processor Technical Reference Manual
7-7