Table 7-1. Hardware Configuration Register (Hwcr) Fields - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual

Table 7-1. Hardware Configuration Register (HWCR) Fields

Bit Mnemonic
31–8 —
7 DDC
6 DIC
5 DBP
4 —
3–1 DC
0 DSPC
Notes:
Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement.
7-4
Description
—
Disable Data Cache
Disable Instruction Cache
Disable Branch Prediction
—
Debug Control
Disable Stopping
Processor Clocks
Function
reserved
Disables data cache.
0 = enabled, 1 = disabled.
Disables instruction cache.
0 = enabled, 1 = disabled.
Disables branch prediction.
0 = enabled, 1 = disabled.
reserved
Debug control bits:
000 Off (disable HWCR debug control).
001 Enable branch-tracing messages. See Section
7.6 on page 7-17.
010 reserved
011 reserved
100 reserved
101 reserved
110 reserved
111 reserved
Disables stopping of internal processor clocks in the
Halt and Stop Grant states.
0 = enabled, 1 = disabled.
18524C/0—Nov1996
Test and Debug