Table 5-27. Banks 0 And 1 - Common Control And Status Register Map; Table 5-28. Bank 1 - Ceir Wakeup Configuration And Control Register Map - AMD Geode SC1200 Data Book

SuperI/O Module
5.6.2 SWC Registers
The SWC registers are organized in two banks. The offsets
are related to a base address that is determined by the
SWC Base Address Register in the logical device configu-
ration. The lower three registers are common to the two
banks while the upper registers (03h-0Fh) are divided as
follows:

Table 5-27. Banks 0 and 1 - Common Control and Status Register Map

Offset Type
00h R/W1C
01h R/W
02h R/W

Table 5-28. Bank 1 - CEIR Wakeup Configuration and Control Register Map

Offset Type
03h R/W
04h ---
05h R/W
06h R/W
07h RO
08h R/W
09h R/W
0Ah R/W
0Bh R/W
0Ch R/W
0Dh R/W
0Eh R/W
0Fh R/W
AMD Geode™ SC1200/SC1201 Processor Data Book
• Bank 0 holds reserved registers.
• Bank 1 holds the CEIR Control Registers.
The active bank is selected through the Configuration Bank
Select field (bits [1:0]) in the Wakeup Configuration Regis-
ter (WKCFG). See Table 5-29 on page 118.
The tables that follow provide register maps and bit defini-
tions for Banks 0 and 1.
Name
WKSR. Wakeup Events Status Register
WKCR. Wakeup Events Control Register
WKCFG. Wakeup Configuration Register
Name
IRWCR. CEIR Wakeup Control Register
RSVD. Reserved
IRWAD. CEIR Wakeup Address Register
IRWAM. CEIR Wakeup Address Mask Register
ADSR. CEIR Address Shift Register
IRWTR0L. CEIR Wakeup, Range 0, Low Limit Register
IRWTR0H. CEIR Wakeup, Range 0, High Limit Register
IRWTR1L. CEIR Wakeup, Range 1, Low Limit Register
IRWTR1H. CEIR Wakeup, Range 1, High Limit Register
IRWTR2L. CEIR Wakeup, Range 2, Low Limit Register
IRWTR2H. CEIR Wakeup, Range 2, High Limit Register
IRWTR3L. CEIR Wakeup, Range 3, Low Limit Register
IRWTR3H. CEIR Wakeup, Range 3, High Limit Register
32579B
Reset
Value
00h
03h
00h
Reset
Value
00h
---
00h
E0h
00h
10h
14h
07h
0Bh
50h
64h
28h
32h
117