AMD K5 Technical Reference Manual page 131

18524C/0—Nov1996
Signal Overview
INTR Interrupts—The processor disables INTR interrupts
during all software interrupts (that is, INTn instructions that
vector through interrupt gates or through task gates that
reference a TSS with IF cleared in its EFLAGS image). It
does this by automatically clearing the IF bit in EFLAGS. If
system logic can leave the INTR signal asserted after the
INTR service routine is entered, the interrupt vector
returned by system logic during the Interrupt acknowledge
operation must be for an interrupt gate or for a task gate
that references a TSS with IF cleared. (Software may set
the IF flag again upon entering the service routine.)
NMI Interrupts—The processor disables NMI interrupts
until the IRET of the NMI service routine.
Debug Breakpoints—After a debug breakpoint exception,
the debug service routine can disable debug exceptions for
one instruction by setting the resume flag (RF) in EFLAGS
to 1 to prevent restarted instructions from generating
another debug fault.
Table 5-3 shows the characteristics of interrupts and excep-
tions and the priority with which the processor recognizes
them. The term priority means two things here:
Simultaneous Interrupts—The order in which a single inter-
rupt or exception is selected for recognition if all occur
simultaneously, and
Latched Interrupts—The order in which latched interrupts
(any of the four edge-triggered interrupts, FLUSH, SMI,
INIT, or NMI) are recognized when the processor becomes
interruptible again after it recognizes a prior interrupt or
exception. By contrast, the term priority does not mean the
order in which level-sensitive interrupts (BUSCHK, R/S,
INTR, and STPCLK) are nested if one such interrupt occurs
while the processor is responding to another interrupt.
Interrupts are themselves interruptible only if they have a
software component, such as a service routine. All other inter-
rupts complete their action before the processor recognizes
another interrupt. Lower-priority interruptible interrupts can
be interrupted by higher-priority interrupts or exceptions at
their point of interruptibility, as shown in the right-most column
of Table 5-3, which is always on an instruction boundary.
AMD-K5 Processor Technical Reference Manual
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