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AMD-K5 Processor Technical Reference Manual
Table 5-2. Conditions for Driving and Sampling Signals
Bus Cycles or Cache Accesses
Signal
AHOLD
I
BOFF
I
BREQ
O
HLDA
O
HOLD
I
A20M
I
10 10 10 10
2
I/O
A31–A3
AP
I/O
ADS
O
ADSC
O
APCHK
O
BE7–BE0
D/C
O
EWBE
I
LOCK
O
M/IO
O
18
I
18 18 18
NA
SCYC
O
13 13
W/R
O
5-8
Conditions under which signals are meaningfully driven or sampled
38
Bus Arbitration
23
38
39
Address and Address Parity
10
44 19
19
38
38 37
38 37
7
38 37
Cycle Definition and Control
38 37
37
26 26
38
1
—
38 37
13
38 37
Arbitration
States and Modes
—
—
35
—
35
10 10 10
7
4
4
3
3
7
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
16
3
3
16
3
3
3
3
16
16
3
3
16
13
16
3
3
18524C/0—Nov1996
Reset,
8
Debug
10
3
3
3
3
3
3
3
3
3
3
18
13
3
Bus Interface
3
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