Inquire Cycles - AMD K5 Technical Reference Manual

AMD-K5 Processor Technical Reference Manual
6.2.4

Inquire Cycles

6-12
Repetitive writes to the same location are slower than in
•
writeback mode.
No updates to the data cache are hidden from the sys-
•
tem.
When returning from SMM with SMM memory cache-
•
able, there is no need to write back modified lines in the
data cache, so the mode transition may be faster. (Both
caches, however, must be invalidated.)
Writeback Protocol:
Repetitive writes to the same location are faster than in
•
writethrough mode.
Updates that hit exclusive or modified lines in the data
•
cache are hidden from the system.
When returning from SMM, in which SMM memory is
•
cacheable, modified lines in the data cache must be writ-
ten back before invalidating both caches, so the mode
transition may be slower.
In single-processor systems with no other caching master, WB/
WT is typically tied High. This allows the processor to cache all
cacheable reads in the exclusive state, and all cacheable writes
update only the cache. In systems with multiple caching mas-
ters, WB/WT can be generated after inquire cycles to all other
caching masters by the logical OR of HIT from all of the mas-
ters. This allows the processor to cache reads in the exclusive or
modified state only if no other master has a copy.
The write-once protocol, as described in Section 6.2.6 on page
6-19, combines the system visibility features of pure
writethrough and writeback protocols. While the writeback
function can support higher performance in systems with a sin-
gle caching master, the writethrough function is required for
certain transitions in the write-once protocol in systems with
multiple caching masters.
System logic maintains coherency between external caching
devices and the processor's internal caches by driving inquire
cycles to the processor during shared-memory accesses by
other caching masters. Inquire cycles are often called snoops or
invalidations, but these terms are too general to clearly differ-
18524C/0—Nov1996
System Design