Figure 5-18. Uart Mode Register Bank Architecture; Table 5-37. Bank 0 Register Map - AMD Geode SC1200 Data Book

SuperI/O Module
5.8.2 UART Functionality (SP1 and SP2)
Both SP1 and SP2 provide UART functionality. The
generic SP1 and SP2 support serial data communication
with remote peripheral device or modem using a wired
interface. The functional blocks can function as a standard
16450, 16550, or as an Extended UART.
5.8.2.1 UART Mode Register Bank Overview
Four register banks, each containing eight registers, con-
trol UART operation. All registers use the same 8-byte
address space to indicate offsets 00h through 07h. The
BSR register selects the active bank and is common to all
banks. See Figure 5-18.
5.8.2.2 SP1 and SP2 Register and Bit Maps for UART
Functionality
The tables in this subsection provide register and bit maps
for Banks 0 through 3.
Offset Type
00h RO
W
01h R/W
02h RO
R/W
03h W
R/W
04h R/W
05h R/W
06h R/W
07h R/W
R/W
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 132.
AMD Geode™ SC1200/SC1201 Processor Data Book

Table 5-37. Bank 0 Register Map

Name
RXD. Receiver Data Port
TXD. Transmitter Data Port
IER. Interrupt Enable
EIR. Event Identification (Read Cycles)
FCR. FIFO Control (Write Cycles)
1
LCR . Line Control
1
BSR .Bank Select
MCR. Modem/Mode Control
LSR. Link Status
MSR. Modem Status
SPR. Scratchpad
ASCR. Auxiliary Status and Control
32579B
Bank 3
Bank 2
Bank 1
Bank 0
Offset 07h
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
Offset 02h
Offset 01h
Offset 00h
16550 Banks
Figure 5-18. UART Mode Register Bank
Architecture
Common
Register
Throughout
All Banks
131