Table 8-4: Lpc Cycle List And Data Direction - AMD SP5100 Data Book

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read/write. It supports up to two bus masters and 7 DMA channels. A bus master or DMA agent uses
LDRQ pin to assert bus master or DMA request. The host controller uses LFRAME# to indicate the start
or termination of a cycle. The following table shows a list of cycles supported by the host controller,
initiator, data flow direction, and their PCI counterparts.

Table 8-4: LPC Cycle List and Data Direction

Cycle Size (bytes)
Memory read 1
Memory write 1
I/O read 1
I/O write 1
DMA read 1,2,4
DMA write 1,2,4
BM Memory 1,2,4
read
BM Memory 1,2,4
write
BM I/O read 1,2,4
BM I/O write 1,2,4
The host controller has a SERIRQ (Serial IRQ) pin, which is used by peripherals that require interrupt
support. All legacy interrupts are serialized on this pin, and then decoded by the host controller and sent
to the interrupt controller for processing. Please refer to the Serial IRQ Specification (Rev 5.4) for detailed
description on serial IRQ protocol.
Initiator Data Direction
Host P-2-Host
Host Host-2-P
Host P-2-Host
Host Host-2-P
Peripheral Host-2-P
Peripheral P-2-Host
Peripheral Host-2-P
Peripheral P-2-Host
Peripheral Host-2-P
Peripheral P-2-Host
Functional Description
AMD SP5100 Databook
PCI counterpart
MemRead to LPC range
MemWrit to LPC range
IORead to LPC range
IOWrit to LPC range
DMA Cntrl Setup; DMA data fetch
DMA Cntrl Setup; DMA data store
DMA Cntrl Setup; DMA data fetch
DMA Cntrl Setup; DMA data store
DMA Cntrl Setup; IO data fetch
DMA Cntrl Setup; IO data store
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