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Display Timing Examples
VCLKOUT
VDOUT[9−2]
VDOUT[19−12]
63
5655
Y 7
Y 71
Y FIFO
63
5655
Cb 7
Cb FIFO
63
5655
Cr 7
Cr FIFO
4.9
Display Timing Examples
The following are examples of display output for several modes of operation.
4.9.1 Interlaced BT.656 Timing Example
This section shows an example of BT.656 display output for a 704 x 408 interlaced output image as might
be generated by MPEG decoding.
The horizontal output timing is shown in
pipeline delay between the internal counter changing and the output on external pins. The actual delay
can be longer or shorter as long as it is consistent within any display mode. The BT.656 active line is
720-pixels wide.
Figure 4-25
IMGHOFFx of 8 pixels.
The HBLNK and HSYNC signals are shown as they would be output for active-low operation. Note that
only one of the two signals is actually available externally. The HBLNK inactive edge occurs either on
sample 856 coincident with the start of SAV or on sample 0 (after SAV) if the HBDLA bit is set. For true
BT.656 operation, neither HBLNK nor HSYNC would be used.
The IPCOUNT operation follows the description in
displayed pixel (FPCOUNT = IMGHOFFx) and stops counting at the last displayed pixel (IPCOUNT =
IMGHSIZEx). The operation during non-display time is not a requirement, it could continue counting until
the next FPCOUNT = IMGHOFFx point or it could reset immediately after IMGHSIZEx or when FPCOUNT
is reset.
VDOUT shows the output data and switching between EAV, Blanking Data, SAV, Default Data, and FIFO
Data. It is assumed that the DVEN bit in VDCTL is set to enable the default output.
110
Video Display Port
Figure 4-24. Display Line Boundary Example
IPCOUNT = IMGSIZE(78)
Line n
4847
4039
Y 6
Y 5
Y 4
Y 77
Y 76
Y 70
Y 69
Y 68
4847
4039
Cb 6
Cb 5
Cb 4
Cb 38
Cb 37
Cb 36
4847
4039
Cr 6
Cr 5
Cr 4
Cr 38
Cr 37
Cr 36
Little-Endian Packing
Figure
shows the 704-pixel image window centered in the screen that results in an
32
31
2423
1615
Y 3
Y 2
Y 75
Y 74
Y 67
Y 66
32
31
2423
1615
Cb 3
Cb 2
Cb 35
Cb 34
32
31
2423
1615
Cr 3
Cr 2
Cr 35
Cr 34
4-25. This diagram assumes that there is a two VCLK
Section
4.1.2. IPCOUNT resets to 0 at the first
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8 7
0
Y 1
Y 0
Line n+1
Y 73
Y 72
Line n
Y 65
Y 64
8 7
0
Line n+1
Cb 1
Cb 0
Cb 33
Cb 32
Line n
8 7
0
Cr 1
Cr 0
Line n+1
Cr 33
Cr 32
Line n
SPRUEM1 – May 2007
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