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Ancillary Data Display
cd
ab
Leading edge
replicated chroma
samples
Cb'
= (-3Cb
+ 33Cb
+ 101Cb
a
cd
ab
Cr'
= (-3Cr
+ 33Cr
+ 101Cr
a
cd
ab
Cb'
= (-3Cb
+ 101Cb
b
ab
Cr'
= (-3Cr
b
ab
Cb'
= (-3Cb
c
Cr'
= (-3Cr
c
Cb'
4.5
Ancillary Data Display
The following sections discuss ancillary data display. No special provisions are made for the display of
horizontal ancillary (HANC) or vertical ancillary (VANC), also called vertical blanking interval (VBI), data.
4.5.1 Horizontal Ancillary (HANC) Data Display
HANC data can be displayed using the normal video display mechanism by programming IMGHSIZEn to
occur prior to the SAV code. The HANC data including the ancillary data header must be part of the
YCbCr separated data in the FIFOs. The VCTHRLD value and EDMA size must be programmed to
comprehend the additional samples. You must disable scaling and chroma re-sampling when including the
display of HANC data to prevent data corruption.
4.5.2 Vertical Ancillary (VANC) Data Display
VANC (or VBI) data is commonly used for such features as teletext and closed-captioning. No special
provisions are made for the display of VBI data. VBI data may be displayed using the normal display
mechanism by programming IMGVOFF to occur before the first line of active video on the first line of
desired VBI data. Note that the VBI data must be YCbCr separated. You must disable scaling and chroma
re-sampling when the display of VBI data is desired or the data will be corrupted by the filters.
4.6
Raw Data Display Mode
The raw data display modes are intended to output data to a RAMDAC or other D/A-type device. This is
typically RGB formatted data. No timing information is inserted into the output data stream; instead,
selectable control signals are output to indicate timing. Raw data display includes a synchronized dual
channel option. This allows channel B to output a separate data stream using the same clock and control
as channel A. This mode is useful when used with a second video port in systems that require 24-bit RGB
output.
The raw data mode uses a single FIFO of 5120 bytes for storage of output data. The FIFO is filled by
EDMAs writing to the Y FIFO destination register A (YDSTA). EDMAs are requested using the YEVTA
event. In raw sync mode (RSYNC bit is set), the FIFO is split into 2560-byte channel A and B buffers. The
channel B FIFO is filled by EDMAs using the Y FIFO destination register B (YDSTB) as a destination.
Both YEVTA and YEVTB events are generated using the channel A timing control.
106
Video Display Port
Figure 4-20. Interspersed Chroma Edge Replication
a
ab
b
c
cd
Horizontal Image Size
a
a'
b
b'
c
c'
-3Cb
)/128
ab
cd
-3Cr
)/128
ab
cd
+ 33Cb
-3Cb
)/128
ab
cd
ef
+ 101Cr
+ 33Cr
-3Cr
)/128
ab
cd
ef
+ 33Cb
+ 101Cb
-3Cb
)/128
ab
ab
cd
ef
+ 33Cr
+ 101Cr
-3Cr
)/128
ab
ab
cd
ef
= (-3Cb
+ 101Cb
+ 33Cb
-3Cb
d
ab
cd
ef
gh
Cr'
= (-3Cr
+ 101Cr
+ 33Cr
-3Cr
d
ab
cd
ef
gh
d
w
wx
x
y
yz
d
w
w'
x
x'
y
Cb'
= (-3Cb
y
Cr'
= (-3Cr
y
Cb'
= (-3Cb
+ 101Cb
x
uv
Cr'
= (-3Cr
+ 101Cr
x
uv
)/128
Cb'
= (-3Cb
+ 33Cb
+ 101Cb
w
st
uv
)/128
Cr'
= (-3Cr
+ 33Cr
+ 101Cr
w
st
uv
z
yz
wx
Trailing edge
y'
z
z'
replicated chroma
samples
Cb'
= (-3Cb
+ 101Cb
+ 33Cb
-3Cb
z
wx
yz
yz
Cr'
= (-3Cr
+ 101Cr
+ 33Cr
-3Cb
z
wx
yz
yz
wx
+ 33Cb
+ 101Cb
-3Cb
)/128
uv
wx
yz
yz
+ 33Cr
+ 101Cr
-3Cb
)/128
uv
wx
yz
yz
+ 33Cb
-3Cb
)/128
wx
yz
yz
+ 33Cr
-3Cr
)/128
wx
yz
yz
-3Cb
)/128
wx
yz
-3Cr
)/128
wx
yz
SPRUEM1 – May 2007
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www.ti.com
)/128
wz
)/128
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