Timing Of An Ac97-Standard Data Transfer Near Frame Synchronization - Texas Instruments TMS320VC5501 Reference Manual

Frame Phases
Figure 2−10. Timing of an AC97-Standard Data Transfer Near Frame Synchronization
CLKR
FSR
Á Á
DR P2W12B1
Á Á
2-14 McBSP Operation
1-bit data delay
P2W12B0 P1W1B15
PxWyBz = Phase x Word y Bit z
Note:
On the TMS320VC5501 and TMS320VC5502 devices, if a 0-bit delay and
an external clock are used, the transfer shown in Figure 2−9 can only be
achieved if the frame-sync ignore bit is set to 1. If the frame-sync ignore bit
is 0, an additional clock cycle is required between frames.
P1W1B14
P1W1B13
P1W1B12
SPRU592E