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GPIO Registers
5.1.5 Video Port Pin Data Input Register (PDIN)
PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin's input
buffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit.
The read-only video port pin data input register (PDIN) is shown in
31
23
22
Reserved
PDIN22
R-0
R-0
15
14
PDIN15
PDIN14
R-0
R-0
7
6
PDIN7
PDIN6
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-6. Video Port Pin Data Input Register (PDIN) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PDIN22
OF(value)
DEFAULT
VCTL3LO
VCTL3HI
21
PDIN21
OF(value)
DEFAULT
VCTL2LO
VCTL2HI
20
PDIN20
OF(value)
DEFAULT
VCTL1LO
VCTL1HI
19-2
PDIN[19-2]
OF(value)
DEFAULT
VDATAnLO
VDATAnHI
(1)
For CSL implementation, use the notation VP_PDIN_PDINn_symval
158
General-Purpose I/O Operation
Figure 5-5. Video Port Pin Data Input Register (PDIN)
Reserved
21
20
PDIN21
PDIN20
R-0
R-0
13
12
PDIN13
PDIN12
R-0
R-0
5
4
PDIN5
PDIN4
R-0
R-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
PDIN22 bit returns the logic level of the VCTL3 pin.
0
Pin is logic low.
1
Pin is logic high.
PDIN21 bit returns the logic level of the VCTL2 pin.
0
Pin is logic low.
1
Pin is logic high.
PDIN20 bit returns the logic level of the VCTL1 pin.
0
Pin is logic low.
1
Pin is logic high.
PDIN[19-2] bit returns the logic level of the corresponding VDATA[n] pin.
0
Pin n is logic low.
1
Pin n is logic high.
Figure 5-5
R-0
19
18
PDIN19
PDIN18
R-0
R-0
11
10
Reserved
Reserved
R-0
R-0
3
2
PDIN3
PDIN2
R-0
R-0
www.ti.com
and described in
Table
5-6.
24
17
16
PDIN17
PDIN16
R-0
R-0
9
8
PDIN9
PDIN8
R-0
R-0
1
0
Reserved
Reserved
R-0
R-0
SPRUEM1 – May 2007
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