Examples Of The Detectability Of Write Conflicts By The Assembler - Texas Instruments TMS320C6000 Series Reference Manual

Resource Constraints
Figure 3–3. Examples of the Detectability of Write Conflicts by the Assembler
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However, this code sequence is valid:
MPY .M1 A0,A1,A2
|| ADD .L1 A4,A5,A2
Figure 3–3 shows different multiple-write conflicts. For example, ADD and
SUB in execute packet L1 write to the same register. This conflict is easily de-
tectable.
MPY in packet L2 and ADD in packet L3 might both write to B2 simultaneously;
however, if a branch instruction causes the execute packet after L2 to be
something other than L3, a conflict would not occur. Thus, the potential conflict
in L2 and L3 might not be detected by the assembler. The instructions in L4
do not constitute a write conflict because they are mutually exclusive. In con-
trast, because the instructions in L5 may or may not be mutually exclusive, the
assembler cannot determine a conflict. If the pipeline does receive commands
to perform multiple writes to the same register, the result is undefined.
L1: ADD.L2
|| SUB.S2
L2: MPY.M2
L3: ADD.L2
L4:[!B0] ADD.L2
|| [B0] SUB.S2
L5:[!B1] ADD.L2
|| [B0] SUB.S2
B5,B6,B7 ; \ detectable, conflict
B8,B9,B7 ; /
B0,B1,B2 ; \ not detectable
B3,B4,B2 ; /
B5,B6,B7 ; \ detectable, no conflict
B8,B9,B7 ; /
B5,B6,B7 ; \ not detectable
B8,B9,B7 ; /