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Table 3-24. TCI Capture Control Register (TCICTL) Field Descriptions (continued)
(1)
Bit
field
symval
3
STEN
OF(value)
DEFAULT
DISABLE
SET
2
CTMODE
OF(value)
DEFAULT
90KHZ
STCLK
1
ERRFILT
OF(value)
DEFAULT
ACCEPT
REJECT
0
Reserved
-
3.13.12 TCI Clock Initialization LSB Register (TCICLKINITL)
The transport stream interface clock initialization LSB register (TCICLKINITL) is used to initialize the
hardware counter to synchronize with the system time clock. .
On receiving the first packet containing a program clock reference (PCR) and the PCR extension value,
the DSP writes the 32 least-significant bits (LSBs) of the PCR into TCICLKINITL. This initializes the
counter to the system time clock. TCICLKINITL should also be updated by the DSP whenever a
discontinuity in the PCR field is detected.
To ensure synchronization and prevent false compare detection, the software should disable the system
time clock interrupt (clear the STEN bit in TCICTL) prior to writing to TCICLKINITL. All bits of the system
time counter are initialized whenever either TCICLKINITL or TCICLKINITM are written.
The TCI clock initialization LSB register (TCICLKINITL) is shown in
Table 3-25
31
LEGEND: R/W = Read/Write; -n = value after reset
Table 3-25. TCI Clock Initialization LSB Register (TCICLKINITL) Field Descriptions
(1)
Bit
field
symval
31-0
INPCR
OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_TCICLKINITL_INPCR_symval
SPRUEM1 – May 2007
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(1)
Value BT.656, Y/C Mode, or Raw Data Mode
System time clock interrupt enable bit.
0
Not used.
Not used.
Counter mode select bit.
0
Not used.
Not used.
Error filtering enable bit.
0
Not used.
Not used.
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Figure 3-32. TCI Clock Initialization LSB Register (TCICLKINITL)
Value
BT.656, Y/C Mode, or Raw Data Mode
0-FFFF FFFFh Not used.
0
Description
Figure 3-32
INPCR
R/W-0
Description
Video Capture Registers
TCI Mode
Setting of the STC bit is disabled.
A valid STC compare sets the STC bit in
VPIS.
The 33-bit PCR portion of the system time
counter increments at 90 kHz (when
PCRE rolls over from 299 to 0).
The 33-bit PCR portion of the system time
counter increments by the STCLK input.
Packets with errors are received and the
PERR bit is set in the timestamp inserted
at the end of the packet.
Packets with errors are filtered out (not
received in the FIFO).
and described in
TCI Mode
Initializes the 32 LSBs of the system
time clock.
Video Capture Port
0
85
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