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Video Port Control Registers
Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued)
(1)
Bit
field
symval
3
SERRA
OF(value)
DEFAULT
DISABLE
ENABLE
2
CCMPA
OF(value)
DEFAULT
DISABLE
ENABLE
1
COVRA
OF(value)
DEFAULT
DISABLE
ENABLE
0
VIE
OF(value)
DEFAULT
DISABLE
ENABLE
2.4.4 Video Port Interrupt Status Register (VPIS)
The video port interrupt status register (VPIS) displays the status of video port interrupts to the DSP. The
interrupt is only sent to the DSP if the corresponding enable bit in VPIE is set. All VPIS bits are cleared by
writing a 1, writing a 0 has no effect.
The video port interrupt status register (VPIS) is shown in
31
23
22
LFDB
SFDB
R/WC-0
R/WC-0
15
14
Reserved
DCNA
R-0
R/WC-0
7
6
LFDA
SFDA
R/WC-0
R/WC-0
LEGEND: R = Read only; WC = Write 1 to clear, a write of 0 has no effect; -n = value after reset
Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions
(1)
Bit
field
symval
31-24 Reserved
-
(1)
For CSL implementation, use the notation VP_VPIS_field_symval
40
Video Port
(1)
Value Description
Channel A synchronization error interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Capture complete on channel A interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Capture overrun on channel A interrupt enable bit.
0
Interrupt is disabled.
1
Interrupt is enabled.
Video port global interrupt enable bit. Must be set for interrupt to be sent to DSP.
0
Interrupt is disabled.
1
Interrupt is enabled.
Figure 2-4. Video Port Interrupt Status Register (VPIS)
Reserved
21
20
VINTB2
VINTB1
R/WC-0
R/WC-0
13
12
DCMP
DUND
R/WC-0
R/WC-0
5
4
VINTA2
VINTA1
R/WC-0
R/WC-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Figure 2-4
and described in
R-0
19
18
SERRB
CCMPB
R/WC-0
R/WC-0
11
10
TICK
STC
R/WC-0
R/WC-0
3
2
SERRA
CCMPA
R/WC-0
R/WC-0
www.ti.com
Table
2-6.
24
17
16
COVRB
GPIO
R/WC-0
R/WC-0
9
8
Reserved
R-0
1
0
COVRA
Reserved
R/WC-0
R-0
SPRUEM1 – May 2007
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