Related Manuals for Texas Instruments DM648 DSP
Summary of Contents for Texas Instruments DM648 DSP
- Page 1 TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide Literature Number: SPRUEK5A October 2007...
- Page 2 SPRUEK5A – October 2007 Submit Documentation Feedback...
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Page 3: Table Of Contents
Preface Introduction Purpose of the Peripheral Features Functional Block Diagram Industry Standard(s) Compliance Statement Peripheral Architecture Clock Control Memory Map Signal Descriptions Protocol Description(s) Memory Width and Byte Alignment Address Mapping DDR2 Memory Controller Interface Refresh Scheduling Self-Refresh Mode 2.10 Reset Considerations 2.11 DDR2 SDRAM Memory Initialization... - Page 4 DDR2 Memory Controller Block Diagram DDR2 Memory Controller Signals DDR2 MRS and EMRS Command Refresh Command ACTV Command DCAB Command DEAC Command DDR2 READ Command DDR2 WRT Command Byte Alignment Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM Logical Address-to-DDR2 SDRAM Address Map DDR2 SDRAM Column, Row, and Bank Access DDR2 Memory Controller FIFO Block Diagram...
- Page 5 DDR2 Memory Controller Signal Descriptions DDR2 SDRAM Commands Truth Table for DDR2 SDRAM Commands Addressable Memory Ranges Bank Configuration Register Fields for Address Mapping DDR2 Memory Controller FIFO Description Refresh Urgency Levels Reset Sources DDR2 SDRAM Mode Register Configuration DDR2 SDRAM Extended Mode Register 1 Configuration SDCFG Configuration DDR2 Memory Refresh Specification SDRFC Configuration...
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Page 6: Preface
C64x DSP with added functionality and an expanded instruction set. SPRUEK5 — TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2 memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The DDR2/mDDR memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices and standard Mobile DDR SDRAM devices. - Page 7 CPU. SPRUEL9 — TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in the TMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speed point-to-point serial interface for connecting to host processors and other VLYNQ compatible devices.
- Page 8 Related Documentation From Texas Instruments SPRUEM2 — TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the Serial Port Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This reference guide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface.
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Page 9: Introduction
Introduction This document describes the DDR2 memory controller in the device. Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memories are not supported. -
Page 10: Industry Standard(S) Compliance Statement
Introduction Figure 1. DDR2 Memory Controller Block Diagram EMIFA DDR2 memory controller PLL2 Other peripherals EDMA controller Boot PLL2 configuration Industry Standard(s) Compliance Statement The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with the exception of the On Die Termination (ODT) feature. The DSP does not include any on-die terminating resistors. -
Page 11: Peripheral Architecture
www.ti.com Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibility through programmable parameters such as the refresh rate, CAS latency, and many SDRAM timing parameters. -
Page 12: Ddr2 Memory Controller Signals
Peripheral Architecture Figure 2. DDR2 Memory Controller Signals Table 1. DDR2 Memory Controller Signal Descriptions Description DDR_D[31:0] Bidirectional data bus. Input for data reads and output for data writes. DDR_A[13:0] External address output. DDR_CS Active-low chip enable for memory space CE0. DDR_CS is used to enable the DDR2 SDRAM memory device during external memory accesses. -
Page 13: Protocol Description(S)
www.ti.com Protocol Description(s) The DDR2 memory controller supports the DDR2 SDRAM commands listed in signal truth table for the DDR2 SDRAM commands. Command Function ACTV Activates the selected bank and row. DCAB Precharge all command. Deactivates (precharges) all banks. DEAC Precharge single command. -
Page 14: Ddr2 Mrs And Emrs Command
Peripheral Architecture 2.4.1 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. -
Page 15: Refresh Command
www.ti.com DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[13:0] DDR_BA[2:0] DDR_DQM[3:0] 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. -
Page 16: Dcab Command
Peripheral Architecture 2.4.4 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). -
Page 17: Ddr2 Read Command
www.ti.com 2.4.5 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0]. -
Page 18: Memory Width And Byte Alignment
Peripheral Architecture 2.4.6 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. -
Page 19: Address Mapping
www.ti.com Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is always right aligned on the data bus. DDR_D[31:24] (Byte Lane 3) Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true regardless of the number of memory devices located on the chip select space. -
Page 20: Logical Address-To-Ddr2 Sdram Address Map For 16-Bit Sdram
Peripheral Architecture SDCFG Bit IBANK PAGESIZE 31:28 Legend: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits; BE = byte enable bits. Figure 12. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM SDCFG Bit IBANK PAGESIZE... -
Page 21: Logical Address-To-Ddr2 Sdram Address Map
www.ti.com Figure 11 shows how the DSP memory map is partitioned into columns, rows, and banks. Note that during a linear access, the DDR2 memory controller increments the column address as the logical address increments. When the DDR2 memory controller reaches a page/row boundary, it moves onto the same page/row in the next bank. -
Page 22: Ddr2 Memory Controller Interface
Peripheral Architecture Figure 14. DDR2 SDRAM Column, Row, and Bank Access Bank 0 0 1 2 3 Row 0 Row 1 Bank 1 Row 2 Row 0 Row 1 Row 2 Row N Row N M is number of columns (as determined by PAGESIZE) minus 1, P is number of banks (as determined by IBANK) minus 1, and N is number of rows (as determined by both PAGESIZE and IBANK) minus 1. -
Page 23: Ddr2 Memory Controller Fifo Block Diagram
www.ti.com Figure 15. DDR2 Memory Controller FIFO Block Diagram Command FIFO Write FIFO Read FIFO Command Data 2.7.1 Command Ordering and Scheduling, Advanced Concept The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput. The goal is to maximize the utilization of the data, address, and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows. - Page 24 Peripheral Architecture Next, the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering: Among all pending reads, selects reads to rows already open. Among all pending writes, selects writes to rows already open. Selects the highest priority command from pending reads and writes to open rows.
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Page 25: Refresh Scheduling
www.ti.com 2.7.3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller. For example, if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that the write completes, when master B attempts to read the software message it may read stale data and therefore receive an incorrect message. -
Page 26: Self-Refresh Mode
Peripheral Architecture Self-Refresh Mode Setting the self refresh (SR) bit in the SDRAM refresh control register (SDRFC) to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low-power mode (self refresh), in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power. When the SR bit is asserted, the DDR2 memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cleared. -
Page 27: 2.11 Ddr2 Sdram Memory Initialization
www.ti.com 2.11 DDR2 SDRAM Memory Initialization DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device. These registers control parameters such as burst type, burst length, and CAS latency. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence described in Section 2.11.3. -
Page 28: 2.12 Interrupt Support
Peripheral Architecture Table 10. DDR2 SDRAM Extended Mode Register 1 Configuration (continued) Mode Mode Register Register Bit Field ODT Value (Rtt) Output Driver Impedance DLL Enable 2.11.2 DDR2 SDRAM Initialization After Reset After a hard or a soft reset, the DDR2 memory controller will automatically start the initialization sequence. The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device(s). -
Page 29: Using The Ddr2 Memory Controller
www.ti.com Using the DDR2 Memory Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices. The steps required to configure the DDR2 memory controller for external memory access are also described. Connecting the DDR2 Memory Controller to DDR2 SDRAM Figure Figure 18, and... -
Page 30: Connecting To Two 16-Bit Ddr2 Sdram Devices
Using the DDR2 Memory Controller Figure 17. Connecting to Two 16-Bit DDR2 SDRAM Devices DDR_CLK DDR_CLK DDR_CKE DDR2 DDR_CS memory DDR_WE controller DDR_RAS DDR_CAS DDR_DQM0 DDR_DQM1 DDR_DQS0 DDR_DQS0 DDR_DQS1 DDR_DQS1 DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_DQM2 DDR_DQM3 DDR_DQS2 DDR_DQS2 DDR_DQS3 DDR_DQS3 DDR_D[31:16] DDR_ODT0 DDR_ODT1 DDR_DQGATE0... -
Page 31: Connecting To A Single 16-Bit Ddr2 Sdram Device
www.ti.com Figure 18. Connecting to a Single 16-Bit DDR2 SDRAM Device DDR_CLK DDR_CLK DDR_CKE DDR2 DDR_CS memory DDR_WE controller DDR_RAS DDR_CAS DDR_DQM0 DDR_DQM1 DDR_DQS0 DDR_DQS0 DDR_DQS1 DDR_DQS1 DDR_BA[2:0] DDR_A[13:0] DDR_D[15:0] DDR_ODT0 DDR_ODT1 DDR_VREF DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 These pins are used as a timing reference during memory reads. For routing rules, see the device-specific data manual. -
Page 32: Connecting To Two 8-Bit Ddr2 Sdram Devices
Using the DDR2 Memory Controller Figure 19. Connecting to Two 8-Bit DDR2 SDRAM Devices DDR_CLK DDR_CLK DDR_CKE DDR2 DDR_CS memory DDR_WE controller DDR_RAS DDR_CAS DDR_DQM0 DDR_DQS0 DDR_DQS0 DDR_BA[2:0] DDR_A[13:0] DDR_D[7:0] DDR_DQM1 DDR_DQS1 DDR_DQS1 DDR_D[15:8] DDR_ODT0 DDR_ODT1 DDR_VREF DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 These pins are used as a timing reference during memory reads. -
Page 33: Configuring Ddr2 Memory Controller Registers To Meet Ddr2 Sdram Specifications
www.ti.com Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By programming the SDRAM Configuration Register (SDCFG), SDRAM Refresh Control Register (SDRFC), SDRAM Timing 1 Register (SDTIM1), and SDRAM Timing 2 Register (SDTIM2), the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D-2A compliant DDR2... -
Page 34: Ddr2 Memory Refresh Specification
Using the DDR2 Memory Controller Table 12 displays the DDR2-533 refresh rate specification. Symbol Therefore, the value for the REFRESH-RATE can be calculated as follows: REFRESH_RATE = 266.5 MHz Table 13 shows the resulting SDRFC configuration. Field Value REFRESH_RATE 3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2) The SDRAM timing 1 register (SDTIM1) and SDRAM timing 2 register (SDTIM2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. -
Page 35: Sdtim2 Configuration
www.ti.com DDR2 SDRAM Data Register Field Sheet Parameter Name Name T_ODT AOND T_SXNR SXNR T_SXRD SXRD T_RTP T_CKE 3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL) The DDR2 memory controller control register (DMCCTL) contains a read latency (RL) field that helps the DDR2 memory controller determine when to sample read data. -
Page 36: Ddr2 Memory Controller Registers
DDR2 Memory Controller Registers DDR2 Memory Controller Registers Table 17 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data manual for the memory address of these registers. Offset Acronym MIDR DMCSTAT SDCFG SDRFC SDTIM1 SDTIM2 BPRIO DMCCTL DSP DDR2 Memory Controller Table 17. -
Page 37: Module Id And Revision Register (Midr)
www.ti.com Module ID and Revision Register (MIDR) The Module ID and Revision register (MIDR) is shown in Figure 20. Module ID and Revision Register (MIDR) Reserved R-0x0 MJ_REV R-0x03 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 18. -
Page 38: Sdram Configuration Register (Sdcfg)
DDR2 Memory Controller Registers SDRAM Configuration Register (SDCFG) The SDRAM configuration register (SDCFG) contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of internal banks, and page size of the external DDR2 memory. Bits 0-14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 (unlocked). - Page 39 www.ti.com Table 20. SDRAM Configuration Register (SDCFG) Field Descriptions (continued) Field Value Description 11-9 CAS latency. The value of this field defines the CAS latency, to be used when accessing connected SDRAM devices. A write to this field will cause the DDR2 Memory Controller to start the SDRAM initialization sequence.
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Page 40: Sdram Refresh Control Register (Sdrfc)
DDR2 Memory Controller Registers SDRAM Refresh Control Register (SDRFC) The SDRAM refresh control register (SDRFC) is used to configure the DDR2 memory controller to: Enter and Exit the self-refresh state. Meet the refresh requirement of the attached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands. -
Page 41: Sdram Timing 1 Register (Sdtim1)
www.ti.com SDRAM Timing 1 Register (SDTIM1) The SDRAM timing 1 register (SDTIM1) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. Note that DDR_CLK is equal to the period of the DDR_CLK signal. - Page 42 DDR2 Memory Controller Registers Table 22. SDRAM Timing 1 Register (SDTIM1) Field Descriptions (continued) Field Value Description T_WTR These bits specify the minimum number of DDR_CLK cycles from the last write to a read command, minus 1. The value for these bits can be derived from the t DDR2 memory data sheet.
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Page 43: Sdram Timing 2 Register (Sdtim2)
www.ti.com SDRAM Timing 2 Register (SDTIM2) Like the SDRAM timing 1 register (SDTIM1), the SDRAM timing 2 register (SDTIM2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. See the DDR2 memory data sheet for information on the appropriate values to program each field. The bit fields in the SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register (SDCFG) is unlocked. -
Page 44: Burst Priority Register (Bprio)
DDR2 Memory Controller Registers Burst Priority Register (BPRIO) The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command. -
Page 45: Ddr2 Memory Controller Control Register (Dmcctl)
www.ti.com DDR2 Memory Controller Control Register (DMCCTL) The DDR2 memory controller control register (DMCCTL) resets the interface logic of the DDR2 memory controller. The DMCCTL is shown in Figure 27. DDR2 Memory Controller Control Register (DMCCTL) Reserved R/W-0x0190 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 25. -
Page 46: Appendix A Revision History
Appendix A Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Reference Additions/Modifications/Deletions Global Revised all signal names to match the data manual Section 2.3 Changed fourth bullet. Figure 2 Changed Figure Figure 3 Changed Figure... -
Page 47: Important Notice
TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...