Video Display Field 1 Image Size Register (Vdimgsz1); Video Display Field 1 Image Size Register (Vdimgsz1) Field Descriptions - Texas Instruments TMS320DM648 User Manual

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Table 4-14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions (continued)
(1)
Bit field symval
11-0 IMGHOFF1 OF(value)
DEFAULT

4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)

The video display field 1 image size register (VDIMGSZ1) defines the field 1 image area and specifies the
size of the displayed image within the active display.
The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image.
Displayed image pixel output stops when IPCOUNT = IMGHSIZE1. The default output values or blanking
values are output for the remainder of the active line.
The image line counter (ILCOUNT) counts displayed image lines. Displayed image output stops when
ILCOUNT = IMGVSIZE1. The default output values or blanking values are output for the remainder of the
active field.
The video display field 1 image size register (VDIMGSZ1) is shown in
Table 4-15.
Figure 4-40. Video Display Field 1 Image Size Register (VDIMGSZ1)
31 28
Reserved
R-0
15 12
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-15. Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions
(1)
Bit field symval
31-28 Reserved -
27-16 IMGVSIZE1 OF(value)
DEFAULT
15-12 Reserved -
11-0 IMGHSIZE1 OF(value)
DEFAULT
(1)
For CSL implementation, use the notation VP_VDIMGSZ1_field_symval
SPRUEM1 – May 2007
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(1)
Value BT.656 and Y/C Mode
0-FFFh Specifies the display image horizontal
offset in pixels from the start of each line offset in pixels from the start of each line
of active video in field 1. This must be an of active video in field 1.
even number (the LSB is treated as 0).
0
27
11
(1)
Value BT.656 and Y/C Mode
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh Specifies the display image height in lines.
0
0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
0-FFFh Specifies the display image width in
pixels. This number must be even (the
LSB is treated as 0).
0
Description
Raw Data Mode
Specifies the display image horizontal
Figure 4-40 and described in
IMGVSIZE1
R/W-0
IMGHSIZE1
R/W-0
Description
Raw Data Mode
Specifies the display image width in
pixels.
Video Display Registers
16
0
Video Display Port 133