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memory and parallel I/O interface timing
timing requirements for a memory read (MSTRB = 0) [H = 0.5 t
t a(A)M
Access time, read data access from address valid
t a(MSTRBL)
Access time, read data access from MSTRB low
t su(D)R
Setup time, read data before CLKOUT low
t h(D)R
Hold time, read data after CLKOUT low
t h(A-D)R
Hold time, read data after address invalid
t h(D)MSTRBH Hold time, read data after MSTRB high
† Address, PS, and DS timings are all included in timings referenced as address.
switching characteristics over recommended operating conditions for a memory read
†
(MSTRB = 0)
(see Figure 13)
Delay time, CLKOUT low to address valid ‡
t d(CLKL-A)
Delay time, CLKOUT high (transition) to address valid §
t d(CLKH-A)
t d(CLKL-MSL)
Delay time, CLKOUT low to MSTRB low
t d(CLKL-MSH)
Delay time, CLKOUT low to MSTRB high
Hold time, address valid after CLKOUT low ‡
t h(CLKL-A)R
Hold time, address valid after CLKOUT high §
t h(CLKH-A)R
† Address, PS, and DS timings are all included in timings referenced as address.
‡ In the case of a memory read preceded by a memory read
§ In the case of a memory read preceded by a memory write
FIXED POINT DIGITAL SIGNAL PROCESSOR
PARAMETER
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320VC5402
SPRS079E – OCTOBER 1998 – REVISED AUGUST 2000
†
]
(see Figure 13)
c(CO)
MIN
6
–2
0
0
MIN
–2
–2
–1
–1
–2
–2
MAX
UNIT
2H–7
ns
2H–8
ns
ns
ns
ns
ns
MAX
UNIT
3
ns
3
ns
3
ns
3
ns
3
ns
3
ns
39
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