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Note:
The VPRST bit may take several clock cycles to clear to 0. The VPRST bit should be
polled to make sure the bit is cleared prior to writing to the video port registers.
Once the port is configured and the VPHLT bit is cleared, the setting of other VPCTL bits
(except VPRST) is disabled. The VCLK2 output may also be driven at this time, if display
mode is selected. VCTL1-3 must remain in a high-impedance state unless enabled as
GPIO, since internal/external sync is selected through VDCTL.
2.1.4 Capture Channel Reset
A software reset may be performed on a single capture channel by setting the RSTCH bit in VCxCTL. This
reset requires that the channel VCLKIN be transitioning. On capture channel reset:
No new EDMA events are generated.
Peripheral bus accesses are acknowledged (RREADY returned) to prevent EDMA lock-up. (Any value
returned on reads).
Channel capture registers are set to their default values.
Channel capture FIFO is flushed (pointers reset).
The VCEN bit in VCxCTL is cleared to 0.
The RSTCH bit self-clears to 0 after completion of the above.
Once the port is configured and the VCEN bit is set, the setting of other VCxCTL bits (except VCEN,
RSTCH, and BLKCAP) is prohibited and the capture counters begin counting. When BLKCAP is cleared,
data capture and event generation may begin.
2.1.5 Display Channel Reset
A software reset may be performed on the display channel by setting the RSTCH bit in VDCTL. This reset
requires that the channel VCLKIN be transitioning. On display channel reset:
No new EDMA events are generated.
Peripheral bus accesses are acknowledged (WREADY returned) to prevent EDMA lock-up. (Write data
may be written into the FIFO or discarded.)
Channel display registers are set to their default values.
Channel display FIFO is flushed (pointers reset).
The VDEN bit in VDCTL is cleared to 0.
The RSTCH bit self-clears to 0 after completion of the above.
Once the port is configured and the VDEN bit is set, the setting of other VDCTL bits (except VDEN,
RSTCH, and BLKDIS) is prohibited and the display counters begin counting. Data outputs are driven (with
default value, blanking, and control codes as appropriate and any control outputs are driven). When the
BLKDIS bit is cleared, event generation may begin and FIFO data displayed.
2.2
Interrupt Operation
The video port generates an interrupt to the DSP core after any of the following events occur:
Capture complete (CCMPx) bit is set.
Capture overrun (COVRx) bit is set.
Synchronization byte error (SERRx) bit is set.
Vertical interrupt (VINTxn) bit is set.
Short field detect (SFDx) bit is set.
Long field detect (LFDx) bit is set.
STC absolute time (STC) bit is set.
STC tick counter expired (TICK) bit is set.
Display complete (DCMP) bit is set.
Display under-run (DUND) bit is set.
SPRUEM1 – May 2007
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Interrupt Operation
Video Port
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