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5. Write to VCxTHRLD to set the capture threshold. The threshold needs to be set in units of double
word. One double word is equal to 8 bytes. Every time the number of received bytes reaches the
number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx is generated
by the video capture module.
6. Configure a EDMA channel to move data from YSRCx to a destination in the DSP memory. The
channel transfers should be triggered by the YEVTx. The size of the transfers should be set
appropriately during the configuration of the EDMA channel parameters. The EDMA must start on a
double word boundary and move an even number of words.
7. Write to the video port interrupt enable register (VPIE) to enable overrun (COVRx) and capture
complete (CCMPx) interrupts, if desired.
8. If raw data synchronization is desired, set the startup synchronization enable (SSE) bit in VCxSTRT1.
9. Write to VCxCTL to:
Set capture mode (CMODE = x1x for raw data mode).
Choose capture operation (CON, FRAME bits).
Set VCEN bit to enable capture.
10. Capture starts when the ICAPEN signal is asserted and VCEN = 1. Data is captured on every
VCLKINx rising edge when CAPENx is active. EDMA events (YEVTx) are generated as triggered by
VCxTHRLD1. When a complete data block has been captured (DCOUNT = VCYSTOP and VCXSTOP
combined value), the FRMC bit in VCxSTAT is set causing the CCMPx bit in VPIS to be set. This
generates a DSP interrupt, if CCMPx is enabled in VPIE.
11. If continuous capture is enabled, the video port begins capturing again on the next VCLKIN rising
edge when CAPEN is valid. If noncontinuous capture is enabled, the next data block is captured during
which the DSP must clear the FRMC bit or further capture is disabled. If single frame capture is
enabled, capture is disabled until the DSP clears the FRMC bit (at which point, raw data sync must
again be performed if enabled).
3.11.1 Handling FIFO Overrun Condition in Raw Data Mode
In case of a FIFO overrun, the COVRx bit is set in VPIS. This condition initiates an interrupt to the DSP, if
the overrun interrupt is enabled (setting the COVRx bit in VPIE enables overrun interrupt).
The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure EDMA
channel settings. The EDMA channel must be reconfigured for capture of the next frame since the current
frame transfer failed. Setting the BLKCAP bit flushes the capture FIFO and blocks EDMA events for the
channel. As long as the BLKCAP bit is set, the video capture channel ignores the incoming data but the
internal data counter continues counting.
The BLKCAP bit should be cleared to 0 in order to continue capture. Clearing the BLKCAP bit takes effect
in the subsequent frame after a raw data sync period is detected on CAPENx. (EDMA events are still
going to be blocked in the frame in which the BLKCAP bit is cleared.)
3.12 Capturing Data in TCI Capture Mode
In order to capture data in TCI capture mode, the following steps are needed:
1. Set VCASTOP1 to specify size of a data packet to be captured (VCXSTOP sets the lower 12 bits and
VCYSTOP sets the upper 12 bits of the data packet).
2. Write to VCxTHRLD to set the capture threshold to the data packet size. Every time the number of
received bytes reaches the number specified by the VCTHRLD1 bits, a YEVTx is generated by the
video capture module.
3. Configure an EDMA channel to move data from YSRCA to a destination in the DSP memory. The
channel transfers should be triggered by the YEVT. The size of the transfers should be set to the data
packet size + 8 bytes of timestamp information. The EDMA must start on a double-word boundary and
move an even number of words.
4. Write to TCICTL to:
Set TCI capture mode (TCMODE = 0 for parallel data, 1 for serial data).
Select counter mode (TCMODE).
Enable error packet filtering (ERRFILT) if desired.
SPRUEM1 – May 2007
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Capturing Data in TCI Capture Mode
Video Capture Port
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