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Related Manuals for Texas Instruments TMS320VC5509A
Summary of Contents for Texas Instruments TMS320VC5509A
- Page 1 Distributed by: www.Jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Jameco Part Number 1519867-Errata...
- Page 2 TMS320VC5509A Digital Signal Processor Silicon Errata SPRZ200E June 2003 − Revised April 2008 Copyright 2005, Texas Instruments Incorporated...
- Page 3 TMS320VC5509A Silicon Errata SPRZ200E REVISION HISTORY This revision history highlights the technical changes made to SPRZ200D to generate SPRZ200E. Scope: Changes to Advisory PM_1 Repeated Interrupts Durring CLKGEN Domain Idle PAGE(S) ADDITIONS/CHANGES/DELETIONS Updated Section 3.12 Power Management Advisories, Advisory PM_1. Changed the Title from “Repeated Interrupts During CPU Idle”...
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Page 4: Table Of Contents
TMS320VC5509A Silicon Errata SPRZ200E Contents Introduction .................. - Page 5 TMS320VC5509A Silicon Errata SPRZ200E 3.7 Real-Time Clock (RTC) Advisories ............. .
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Page 6: Introduction
TMS320VC5509A Silicon Errata SPRZ200E Introduction This document describes the silicon updates to the functional specifications for the TMS320VC5509A. The updates are applicable to: • TMS320VC5509A (144-pin LQFP, PGE suffix) • TMS320VC5509A (179-pin MicroStar BGA, GHH suffix) The advisory numbers in this document are not always sequential. Some advisory numbers have been removed as they do not apply to the device revisions specified in this document. -
Page 7: Revision Identification
TMS320VC5509A Silicon Errata SPRZ200E Revision Identification The device revision can be determined by the lot trace code marked on the top of the package. The locations for the lot trace codes for the PGE and the GHH packages are shown in Figure 1 and Figure 2, respectively. The location of other markings may vary per device. -
Page 8: Usage Notes
TMS320VC5509A Silicon Errata SPRZ200E Usage Notes Usage Notes highlight and describe particular situations where the device’s behavior may not match the presumed or documented behavior. This may include behaviors that affect device performance or functional correctness. These notes will be incorporated into future documentation updates for the device (such as the device-specific data sheet), and the behaviors they describe will not be altered in future silicon revisions. -
Page 9: Known Design Marginality/Exceptions To Functional Specifications
TMS320VC5509A Silicon Errata SPRZ200E Known Design Marginality/Exceptions to Functional Specifications Summary of Advisories Table 2 provides a quick reference of all advisories by number, silicon revision affected, and lists their respective page location. Table 2. Quick Reference Table Advisory Revision(s) - Page 10 TMS320VC5509A Silicon Errata SPRZ200E Table 2. Quick Reference Table (Continued) Advisory Revision(s) Advisory Page Number Affected Inter-Integrated Circuit (I 2 C) Advisories I2C_3 ARDY Interrupt is not Generated Properly in Non-Repeat Mode if STOP Bit is Set 1.0 and 1.1...
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Page 11: Device-Level Advisories
TMS320VC5509A Silicon Errata SPRZ200E Device-Level Advisories Advisory DL_2 Software Modification of MPNMC Bit is Not Pipeline-Protected Revision(s) Affected: 1.0 and 1.1 Details: Software modification of the MPNMC bit in status register 3 (ST3_55) is not pipeline-protected so changes to the device memory map may not become valid before the instructions that immediately follow the modification. -
Page 12: First Word Of Data On Consecutive Dma Transmissions Using Mcbsp Is Lost
TMS320VC5509A Silicon Errata SPRZ200E Advisory DL_10 First Word of Data on Consecutive DMA Transmissions Using McBSP is Lost Revision(s) Affected: 1.0 and 1.1 Details: When executing multiple DMA transfers consecutively using the same DMA Transmit Channel and McBSP, an extra DMA TX request generated by the McBSP at the end of the first transfer will not be serviced by the DMA until the next DMA transfer is initiated by the McBSP. -
Page 13: Bootloader Advisories
TMS320VC5509A Silicon Errata SPRZ200E Bootloader Advisories Advisory BL_3 USB Bootloader Returns Incorrect DescriptorType Value When String Descriptors are Requested by the Host Revision(s) Affected: 1.0 and 1.1 Details: When the host requests for the string descriptor, the USB bootloader returns 0x00 for DescriptorType value instead of 0x03. -
Page 14: Direct Memory Access (Dma) Advisories
TMS320VC5509A Silicon Errata SPRZ200E Direct Memory Access (DMA) Advisories Advisory DMA_1 Early Sync Event Stops Block Transfer Revision(s) Affected: 1.0 and 1.1 Details: When a DMA block transfer is initiated by a sync event, if the same sync event occurs before the last element of the block transfer has been completed, an event drop occurs and the channel becomes disabled. -
Page 15: External Memory Interface (Emif) Advisories
TMS320VC5509A Silicon Errata SPRZ200E External Memory Interface (EMIF) Advisories Advisory EMIF_8 ARDY Pin Requires Strong Pullup Resistor Revision(s) Affected: 1.0 and 1.1 Details: When the parallel bus is used to access external memory, a strong pullup resistor is required for the ARDY pin for the asynchronous memory interface. -
Page 16: Emif_10 Block Write Immediately Following A Block Read May Cause Data Corruption
TMS320VC5509A Silicon Errata SPRZ200E Advisory EMIF_10 Block Write Immediately Following a Block Read May Cause Data Corruption Revision(s) Affected: 1.0 and 1.1 Details: When performing a block write immediately following a block read, data may get corrupted. See the example below. -
Page 17: Emif_12 8-Bit Asynchronous Writes On 5509A Emif Not Supported
TMS320VC5509A Silicon Errata SPRZ200E Advisory EMIF_12 8-Bit Asynchronous Writes on 5509A EMIF Not Supported Revision(s) Affected: 1.0 and 1.1 Details: 8-bit asynchronous writes are not supported; however, 8-bit asynchronous reads are supported. Assembler Notification: None Workaround: None Advisory EMIF_13 After Changing CE Control Registers and Disabling SDRAM Clock in Divide-by-8 and... -
Page 18: Emif_14 Setup = 2 Configuration Is Not Valid For Asynchronous Memory
TMS320VC5509A Silicon Errata SPRZ200E Advisory EMIF_14 SETUP = 2 Configuration is not Valid for Asynchronous Memory Revision(s) Affected: 1.0 and 1.1 Details: When using the EMIF in asynchronous memory mode, a read or write SETUP time setting of two clocks actually behaves like timing of one clock of setup time. -
Page 19: Enhanced Host Port Interface (Ehpi) Advisories
TMS320VC5509A Silicon Errata SPRZ200E Enhanced Host Port Interface (EHPI) Advisories Advisory EHPI_5 HPID Read Following a HPID Write While HRDY Low Corrupts the Read Revision(s) Affected: 1.0 and 1.1 Details: Whether in muxed or non-muxed mode, if a data read overlaps with a HRDY low from a previous data write, the EHPI address used for the read access will be the same as the one preceding the data write. -
Page 20: Ehpi_7 Hrdy Is Always Driven
TMS320VC5509A Silicon Errata SPRZ200E Advisory EHPI_7 HRDY is Always Driven Revision(s) Affected: 1.0 and 1.1 Details: HRDY is always driven to the same value as its internal state. This is only a problem when a single system has devices that have ready signals that are used in conjunction with the DSP’s HRDY signal. -
Page 21: Real-Time Clock (Rtc) Advisories
TMS320VC5509A Silicon Errata SPRZ200E Real-Time Clock (RTC) Advisories Advisory RTC_3 RTC Interrupts are Perceived by the User as Happening One Second Before Revision(s) Affected: 1.0 and 1.1 Details: When the user reads the Real Time Clock time register, these register are read one second after the RTC’s internal timer counter register. -
Page 22: Rtc_5
TMS320VC5509A Silicon Errata SPRZ200E Advisory RTC_5 Midnight and Noon Transitions Do Not Function Correctly in 12h Mode Revision(s) Affected: 1.0 and 1.1 Details: The normal transition from Midnight and Noon should be the following: 11:59am → 12:00pm → 12:59pm → 1:00pm 11:59pm →... -
Page 23: Universal Serial Bus (Usb) Advisories
TMS320VC5509A Silicon Errata SPRZ200E Universal Serial Bus (USB) Advisories Advisory USB_2 CPU Might Miss Back-to-Back USB Interrupts When CPU Speed is Less Than or Equal to 24 MHz Revision(s) Affected: 1.0 and 1.1 Details: When the CPU operates with a clock less than or equal to half the USB module clock, back-to-back USB interrupts might be missed by the CPU. -
Page 24: Inter-Integrated Circuit
TMS320VC5509A Silicon Errata SPRZ200E Inter-Integrated Circuit (I C) Advisories Advisory I2C_3 ARDY Interrupt is not Generated Properly in Non-Repeat Mode if STOP Bit is Set Revision(s) Affected: 1.0 and 1.1 Details: In non-repeat mode, if the STP bit of ICMDR is set, the master sends the STOP condition and does not assert ARDY interrupt after sending data. -
Page 25: I2C_6 Bus Busy Bit Does Not Reflect The State Of The I 2 C Bus When The I 2 C Is In Reset
TMS320VC5509A Silicon Errata SPRZ200E Advisory I2C_6 Bus Busy Bit Does Not Reflect the State of the I C Bus When the I C is in Reset Revision(s) Affected: 1.0 and 1.1 Details: The Bus Busy bit (BB) indicates the status of the I C bus. -
Page 26: 3.10 Multichannel Buffered Serial Port (Mcbsp) Advisories
TMS320VC5509A Silicon Errata SPRZ200E 3.10 Multichannel Buffered Serial Port (McBSP) Advisories Advisory MCBSP_1 McBSP May Not Generate a Receive Event to DMA When Data Gets Copied From RSR to DRR Revision(s) Affected: 1.0 and 1.1 Details: When there is heavy peripheral activity, and the DRR is read, a new receive interrupt might not be generated to the DMA when data in the RSR is copied to the DRR. -
Page 27: 3.11 Emulation Advisories
TCK pad on the back side of the board. Similarly, ground for the probe should come from one of the nearby ground pad vias to minimize EMI noise picked up by the probe. Code Composer Studio, TMS320C55x, and C55x are trademarks of Texas Instruments. - Page 28 TMS320VC5509A Silicon Errata SPRZ200E Emulation Prone to Failure Under Certain Situations (Continued) 2.5 V 0.6 V −1 nanoseconds (ns) Figure 3. Bad TCK Transition 2.5 V 0.6 V −1 nanoseconds (ns) Figure 4. Good TCK Transition Workaround: As the problem may be caused by one or more of the above factors, one or more of the steps outlined below may be necessary to fix it: •...
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Page 29: 3.12 Power Management Advisories
TMS320VC5509A Silicon Errata SPRZ200E 3.12 Power Management Advisories Advisory PM_1 Repeated Interrupts During CLKGEN Domain Idle Revision(s) Affected: 1.0 and 1.1 Details: Any external interrupt staying low for an extended period should generate only one interrupt. The interrupt signal should normally be required to go high, then low again before additional interrupts would be generated. -
Page 30: 3.13 Hardware Accelerator Advisories
TMS320VC5509A Silicon Errata SPRZ200E 3.13 Hardware Accelerator Advisories Advisory HWA_1 Pixel Interpolation Hardware Accelerator Revision(s) Affected: 1.0 and 1.1 Details: The pixel interpolation computation is wrong by one pixel unit in “Decoder” mode, when “Rounding Mode” is set to zero and when half-pixel interpolation is performed in the middle of four full-resolution pixels (i.e., in the middle of two rows of pixels). - Page 31 TMS320VC5509A Silicon Errata SPRZ200E Pixel Interpolation Hardware Accelerator (Continued) The routine below describes the M points computation (diagonal interpolation) for a full block: Presetting: is set with the block size (8 or 16 pixels) is pointing to the first element in the block...
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Page 32: Documentation Support
TMS320VC5509A Silicon Errata SPRZ200E Documentation Support For device-specific data sheets and related documentation, visit the TI web site at: http://www.ti.com. For further information regarding the TMS320VC5509A, please see the latest versions of: • TMS320C55x DSP CPU Reference Guide (literature number SPRU371) •... - Page 33 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.