Texas Instruments TMS320DM648 User Manual
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Texas Instruments TMS320DM648 User Manual

Video port/vcxo interpolated control (vic) port
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TMS320DM647/DM648
Video Port/VCXO Interpolated Control (VIC)
Port
User's Guide
Literature Number: SPRUEM1
May 2007

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Summary of Contents for Texas Instruments TMS320DM648

  • Page 1 TMS320DM647/DM648 Video Port/VCXO Interpolated Control (VIC) Port User's Guide Literature Number: SPRUEM1 May 2007...
  • Page 2 SPRUEM1 – May 2007 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Preface Overview Video Port Video Port FIFO 1.2.1 EDMA Interface 1.2.2 Video Capture FIFO Configurations 1.2.3 Video Display FIFO Configurations Video Port Registers Video Port Pin Mapping 1.4.1 VDIN Bus Usage for Capture Modes 1.4.2 VDOUT Data Bus Usage for Display Modes Video Port Pin Multiplexing VideoPort Clocking Video Port...
  • Page 4 3.3.3 Y/C Image Window and Capture 3.3.4 Y/C FIFO Packing BT.656 and Y/C Mode Field and Frame Operation 3.4.1 Capture Determination and Notification 3.4.2 Vertical Synchronization 3.4.3 Horizontal Synchronization 3.4.4 Field Identification 3.4.5 Short and Long Field Detect Video Input Filtering 3.5.1 Input Filter Modes 3.5.2...
  • Page 5 3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM) 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) 3.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM) 3.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) 3.13.19 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) 3.13.20 TCI System Time Clock Ticks Interrupt Register (TCITICKS) 3.14 Video Capture FIFO Registers...
  • Page 6 4.12 Video Display Registers 4.12.1 Video Display Status Register (VDSTAT) 4.12.2 Video Display Control Register (VDCTL) 4.12.3 Video Display Frame Size Register (VDFRMSZ) 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK) 4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
  • Page 7 Operational Details Enabling VIC Port VIC Port Registers 6.5.1 VIC Control Register (VICCTL) 6.5.2 VIC Input Register (VICIN) 6.5.3 VIC Clock Divider Register (VICDIV) SPRUEM1 – May 2007 Submit Documentation Feedback Contents...
  • Page 8 Video Port Block Diagram BT.656 Video Capture FIFO Configuration 8-Bit Raw Video Capture and TCI Video Capture FIFO Configuration Y/C Video Capture FIFO Configuration 16-Bit Raw Video Capture FIFO Configuration BT.656 Video Display FIFO Configuration 8-Bit Raw Video Display FIFO Configuration 8-Bit Locked Raw Video Display FIFO Configuration 16-Bit Raw Video Display FIFO Configuration 1-10...
  • Page 9 3-39 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) 3-40 TCI System Time Clock Ticks Interrupt Register (TCITICKS) NTSC Compatible Interlaced Display SMPTE 296M Compatible Progressive Scan Display Interlaced Blanking Intervals and Video Areas Progressive Blanking Intervals and Video Area Horizontal Blanking and Horizontal Sync Timing Vertical Blanking, Sync and Even/Odd Frame Signal Timing Video Display Module Synchronization Chain...
  • Page 10 4-52 Video Display Event Register (VDDISPEVT) 4-53 Video Display Clipping Register (VDCLIP) 4-54 Video Display Default Display Value Register (VDDEFVAL) 4-55 Video Display Default Display Value Register (VDDEFVAL) - Raw Data Mode 4-56 Video Display Vertical Interrupt Register (VDVINT) 4-57 Video Display Field Bit Register (VDFBIT) 4-58 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)
  • Page 11 Video Capture Signal Mapping Video Display Signal Mapping VDIN Data Bus Usage for Capture Modes VDOUT Data Bus Usage for Display Modes Video Port Control Registers Video Port Control Register (VPCTL) Field Descriptions Video Port Operating Mode Selection Video Port Status Register (VPSTAT) Field Descriptions Video Port Interrupt Enable Register (VPIE) Field Descriptions Video Port Interrupt Status Register (VPIS) Field Descriptions Video Capture Mode Selection...
  • Page 12 Video Display Control Registers Video Display Status Register (VDSTAT) Field Descriptions Video Display Control Register (VDCTL) Field Descriptions Video Display Frame Size Register (VDFRMSZ) Field Descriptions Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions 4-10 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Descriptions 4-11 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions 4-12...

  • Page 13: Preface

    A legend explains the notation used for the properties. – Reserved bits in a register figure designate a bit that is used for future device expansion. Related Documentation From Texas Instruments The following documents describe the TMS320DM647/DM648 Digital Signal Processor (DSP). Copies of these documents are available on the Internet at www.ti.com.
  • Page 14 Related Documentation From Texas Instruments SPRUEK8 — TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guide describes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital Signal Processor (DSP). The I2C peripheral provides an interface between the DSP and other devices compliant with the I2C-bus specification and connected by way of an I2C-bus.
  • Page 15 16-bit configurable, synchronous serial peripheral interface. The SPI is a programmable-length shift register, used for high speed communication between external peripherals or other DSPs. Trademarks SPRUEM1 – May 2007 Submit Documentation Feedback Related Documentation From Texas Instruments Read This First...

  • Page 16: Overview

    This chapter provides an overview of the video port peripheral in the digital signal processors (DSPs). An overview of the video port functions, FIFO configurations, and signal mapping are included. Topic Video Port Video Port FIFO Video Port Registers Video Port Pin Mapping Video Port Pin Multiplexing VideoPort Clocking Overview...

  • Page 17: Video Port

    www.ti.com Video Port The video port peripheral can operate as a video capture port, video display port, or transport channel interface (TCI) capture port. It provides the following functions: Video capture mode: – Capture rate of up to 80 MHZ. –...

  • Page 18: Video Port Block Diagram

    Video Port This document describes the full feature set offered by the video port. See the device-specific datasheet for details about I/O timing information. VCLK1 VCLK2 Timing and VCTL1 control logic VCTL2 VCTL3 BT.656 capture pipeline Y/C video VDIN[19−2] capture pipeline Raw video capture pipeline TSI capture...

  • Page 19: Video Port Fifo

    www.ti.com Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port. The video port operates in conjunction with EDMA transfers to move data between the video port FIFO and external or on-chip memory.

  • Page 20: Video Capture Fifo Configurations

    Video Port FIFO 1.2.2 Video Capture FIFO Configurations During video capture operation, the video port FIFO has one of four configurations depending on the capture mode. For BT.656 operation, the FIFO is split into channel A and B, as shown in FIFO is clocked independently with the channel A FIFO receiving data from the VDIN[9-2] half of the bus and the channel B FIFO receiving data from the VDIN[19-12] half of the bus.

  • Page 21: Bit Raw Video Capture And Tci Video Capture Fifo Configuration

    www.ti.com For 8-bit raw video, the FIFO is split into channel A and B, as shown in independently with the channel A FIFO receiving data from the VDIN[9-2] half of the bus and the channel B FIFO receiving data from the VDIN[19-12] half of the bus. Each channel's FIFO has a separate write pointer and read register (YSRCx).

  • Page 22: Y/C Video Capture Fifo Configuration

    Video Port FIFO For Y/C video capture, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate write pointers and read registers (YSRCA, CBSRCA, and CRSRCA). Y data is received on the VDIN[9-2] half of the bus and Cb/Cr data is received on the VDIN[19-12] half of the bus and de-multiplexed into the Cb and Cr buffers.

  • Page 23: Video Display Fifo Configurations

    www.ti.com For 16-bit raw video, the FIFO is configured as a single buffer, as shown in 16-bit data from the VDIN[19-2] bus. The FIFO has a single write pointer and read register (YSRCA). Figure 1-5. 16-Bit Raw Video Capture FIFO Configuration VDIN[19−2] 1.2.3 Video Display FIFO Configurations During video display operation, the video port FIFO has one of five configurations depending on the...

  • Page 24: Bit Locked Raw Video Display Fifo Configuration

    Video Port FIFO For locked raw video, the FIFO is split into channel A and B. The channels are locked together and use the same clock and control signals. Each channel uses a single buffer and write register (YDSTx) as shown in Figure 1-8.

  • Page 25: Video Port Registers

    www.ti.com For Y/C video display, the FIFO is configured as a single channel split into separate Y, Cb, and Cr buffers with separate read pointers and write registers (YDSTA, CBDST, and CRDST). data is output on the VDOUT[9-2] half of the bus and Cb/Cr data is multiplexed and output on the VDOUT[19-12] half of the bus.

  • Page 26: Video Port Pin Mapping

    Video Port Pin Mapping Video Port Pin Mapping The video port requires 21 external signal pins for full functionality. Pin usage and direction changes depend on the selected operating mode. Pin functionality detail for video capture mode is listed in Table 1-1.

  • Page 27: Vdin Bus Usage For Capture Modes

    www.ti.com 1.4.1 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1-3. VDIN Data Bus Usage for Capture Modes BT.656 Data Bus 8-Bit VDIN19 VDIN18 VDIN17 VDIN16...

  • Page 28: Vdout Data Bus Usage For Display Modes

    Video Port Pin Multiplexing 1.4.2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1-4. Table 1-4. VDOUT Data Bus Usage for Display Modes BT.656 Data Bus 8-Bit...

  • Page 29: Video Port

    This chapter discusses the basic operation of the video port. Included is a discussion of the sources and types of resets, interrupt operation, EDMA operation, external clock inputs, video port throughput and latency, and the video port control registers. Topic Reset Operation Interrupt Operation EDMA Operation...

  • Page 30: Reset Operation

    Reset Operation Reset Operation The video port has several sources and types of resets. The actions performed by these resets and the state of the port following the resets is described in the following sections. 2.1.1 Power-On Reset Power-on reset is an asynchronous hardware reset caused by a chip-level reset operation. The reset is initiated by a power-on reset input to the video port.

  • Page 31: Capture Channel Reset

    www.ti.com Note: The VPRST bit may take several clock cycles to clear to 0. The VPRST bit should be polled to make sure the bit is cleared prior to writing to the video port registers. Once the port is configured and the VPHLT bit is cleared, the setting of other VPCTL bits (except VPRST) is disabled.

  • Page 32: Edma Operation

    EDMA Operation Display complete not acknowledged (DCNA) bit is set. GPIO interrupt (GPIO) bit is set. The interrupt signal is a pulse only and does not hold state. The interrupt pulse is generated only when the number of set flags in VPIS transitions from none to one or more. Another interrupt pulse is not generated by setting additional flag bits.

  • Page 33: Display Edma Event Generation

    www.ti.com 2.3.2 Display EDMA Event Generation Display EDMA events are generated based on the amount of room available in the FIFO. The VDTHRLDn value indicates the level at which the FIFO has room to receive another EDMA. If the FIFO has at least VDTHRLDn locations available, a EDMA event is generated.

  • Page 34: Edma Interface Operation

    Video Port Control Registers 2.3.4 EDMA Interface Operation When the video port is configured for capture (or TCI) mode, it only accepts read requests from the EDMA interface. Write requests are false acknowledged (so the bus does not stall) and the data is discarded. When the video port is configured for display mode, it only accepts write requests.

  • Page 35: Video Port Control Register (Vpctl)

    www.ti.com 2.4.1 Video Port Control Register (VPCTL) The video port control register (VPCTL) determines the basic operation of the video port. Not all combinations of the port control bits are unique. The control bit encoding is shown in Additional mode options are selected using the video capture channel A control register (VCACTL) and video display control register (VDCTL).

  • Page 36: Video Port Operating Mode Selection

    Video Port Control Registers Table 2-2. Video Port Control Register (VPCTL) Field Descriptions (continued) field symval VCT2P OF(value) DEFAULT NONE ACTIVELOW VCT1P OF(value) ACTIVEHIGH NONE ACTIVELOW Reserved OF(value) DEFAULT NONE CAPTURE DISP OF(value) DEFAULT CAPTURE DISPLAY DCHNL OF(value) DEFAULT SINGLE DUAL Table 2-3.

  • Page 37: Video Port Status Register (Vpstat)

    www.ti.com 2.4.2 Video Port Status Register (VPSTAT) The video port status register (VPSTAT) indicates the current condition of the video port. The video port status register (VPSTAT) is shown in Figure 2-2. Video Port Status Register (VPSTAT) LEGEND: R = Read only; -n = value after reset Table 2-4.

  • Page 38: Video Port Interrupt Enable Register (Vpie)

    Video Port Control Registers 2.4.3 Video Port Interrupt Enable Register (VPIE) The video port interrupt enable register (VPIE) enables sources of the video port interrupt to the DSP. The video port interrupt enable register (VPIE) is shown in Figure 2-3. Video Port Interrupt Enable Register (VPIE) LFDB SFDB VINTB2...
  • Page 39 www.ti.com Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) field symval COVRB OF(value) DEFAULT DISABLE ENABLE GPIO OF(value) DEFAULT DISABLE ENABLE Reserved DCNA OF(value) DEFAULT DISABLE ENABLE DCMP OF(value) DEFAULT DISABLE ENABLE DUND OF(value) DEFAULT DISABLE ENABLE TICK OF(value) DEFAULT...

  • Page 40: Video Port Interrupt Status Register (Vpis)

    Video Port Control Registers Table 2-5. Video Port Interrupt Enable Register (VPIE) Field Descriptions (continued) field symval SERRA OF(value) DEFAULT DISABLE ENABLE CCMPA OF(value) DEFAULT DISABLE ENABLE COVRA OF(value) DEFAULT DISABLE ENABLE OF(value) DEFAULT DISABLE ENABLE 2.4.4 Video Port Interrupt Status Register (VPIS) The video port interrupt status register (VPIS) displays the status of video port interrupts to the DSP.
  • Page 41 www.ti.com Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) field symval LFDB OF(value) DEFAULT NONE CLEAR SFDB OF(value) DEFAULT NONE CLEAR VINTB2 OF(value) DEFAULT NONE CLEAR VINTB1 OF(value) DEFAULT NONE CLEAR SERRB OF(value) DEFAULT NONE CLEAR CCMPB OF(value) DEFAULT NONE...
  • Page 42 Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) field symval COVRB OF(value) DEFAULT NONE CLEAR GPIO OF(value) DEFAULT NONE CLEAR Reserved DCNA OF(value) DEFAULT NONE CLEAR DCMP OF(value) DEFAULT NONE CLEAR DUND OF(value) DEFAULT NONE CLEAR...
  • Page 43 www.ti.com Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) field symval LFDA OF(value) DEFAULT NONE CLEAR SFDA OF(value) DEFAULT NONE CLEAR VINTA2 OF(value) DEFAULT NONE CLEAR VINTA1 OF(value) DEFAULT NONE CLEAR SERRA OF(value) DEFAULT NONE CLEAR CCMPA OF(value) DEFAULT NONE...
  • Page 44 Video Port Control Registers Table 2-6. Video Port Interrupt Status Register (VPIS) Field Descriptions (continued) field symval COVRA OF(value) DEFAULT NONE CLEAR Reserved Video Port Value Description Capture overrun on channel A interrupt detected bit. COVRA is set when data in the FIFO was overwritten before being read out (by the EDMA).

  • Page 45: Video Capture Port

    Video capture works by sampling video data on the input pins and saving it to the video port FIFO. When the amount of captured data reaches a programmed threshold level, an EDMA is performed to move data from the FIFO into DSP memory. In some cases, color separation is performed on the incoming video data requiring multiple FIFOs and EDMAs to be used.

  • Page 46: Video Capture Mode Selection

    Video Capture Mode Selection Video Capture Mode Selection The video capture module operates in one of five modes as listed in interface (TCI) selection is made using the TCI bit in the video port control register (VPCTL). The CMODE bits are in the video capture channel x control register (VCxCTL). The Y/C and 16-bit raw capture modes may only be selected for channel A and only if the DCDIS bit in VPCTL is cleared to 0.

  • Page 47: Bt.656 Video Timing Reference Codes

    www.ti.com Table 3-2. BT.656 Video Timing Reference Codes Data Bit Byte (FFh) 9 (MSB) F = 0 during Field 1; F = 1 during Field 2 V = 0 elsewhere; V = 1 during field blanking H = 0 in SAV; H = 1 in EAV P0, P1, P2, and P3: Depends on F, V, and H state.

  • Page 48: Bt.656 Image Window And Capture

    BT.656 Video Capture Mode Table 3-4. Error Correction by Protection Bits (continued) Received P Bits 1011 1100 1101 1110 1111 3.2.3 BT.656 Image Window and Capture The BT.656 format is an interlaced format consisting of two fields. The video port allows capture of one or both fields.

  • Page 49: Bt.656 Data Sampling

    www.ti.com Video Source square pixel 60 Hz/525 lines BT.601 60 Hz/525 lines square pixel 50Hz/625 lines BT.601 50 Hz/625 lines For the BT.656 video capture mode, the FIFO buffer is divided into three sections (three buffers). One section is 1280 bytes deep and is dedicated for storage of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively.

  • Page 50: Y/C Video Capture Mode

    Y/C Video Capture Mode VCLKINA / VCLKINB Cb 0 VDIN[9−2] / VDIN[9−12] Y 31 Y 30 Y 23 Y 22 Y 15 Y 14 Y FIFO Cb 15 Cb 14 Cb 7 Cb 6 Cb FIFO Cr 15 Cr 14 Cr 7 Cr 6 Cr FIFO...

  • Page 51: Y/C Fifo Packing

    www.ti.com For the Y/C video capture mode, the FIFO buffer is divided into three sections (three buffers). One section is 2560 bytes deep and is dedicated for storage of Y data samples. The other two sections are dedicated for storage of Cb and Cr data samples, respectively. The buffers for Cb and Cr samples are each 1280 bytes deep.

  • Page 52: Capture Determination And Notification

    BT.656 and Y/C Mode Field and Frame Operation to which a continuous stream of fields are stored without DSP intervention. In other cases, the DSP may need to modify EDMA pointer addresses after each field or frame is captured. In some applications, only one field may be captured and the other ignored completely, or a frame may need to be ignored in order to have time to process a previous frame.

  • Page 53: Vertical Synchronization

    www.ti.com Table 3-6. BT.656 and Y/C Mode Capture Operation (continued) VCxCTL Bit FRAME 3.4.2 Vertical Synchronization The video port uses a capture window to determine which incoming data samples to capture in each field. The capture module uses a vertical line counter (VCOUNT) to track which video line is currently being received.

  • Page 54: Vcount Operation Example (Exc = 0)

    BT.656 and Y/C Mode Field and Frame Operation VMode 2 and VMode 3 are used for BT.656 or Y/C capture without embedded EAV/SAV codes and allow alignment with either the active or inactive edge of the vertical control signal on VCTL2. This can be a VBLNK or VSYNC signal from the video decoder.

  • Page 55: Horizontal Synchronization

    www.ti.com 3.4.3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel/sample counter is reset. The EXC and HRST bits in VCxCTL allow you to program the event that triggers the start of a line. The encoding of these bits is shown in Table Table 3-8.

  • Page 56: Field Identification

    BT.656 and Y/C Mode Field and Frame Operation Figure 3-6. HCOUNT Operation Example (EXC = 1) VCLKIN VDIN[9−2] Blanking Data HSYNC EXC=1 HRST=0 HCOUNT VCOUNT n−1 EXC=1 HRST=1 HCOUNT VCOUNT AVID EXC=1 HRST=0 HCOUNT VCOUNT EXC=1 HRST=1 HCOUNT VCOUNT 3.4.4 Field Identification In order to properly synchronize to the source data stream and capture the correct fields, field identification needs to be performed.

  • Page 57: Short And Long Field Detect

    www.ti.com The field indicator method uses the FID input directly to determine the current field. This is useful for Y/C data streams that do not have embedded EAV and SAV codes. The FID input is sampled at the start of each field.

  • Page 58: Input Filter Modes

    Video Input Filtering 3.5.1 Input Filter Modes The input filter has four modes of operation: no-filtering, ½ scaling, chrominance re-sampling, and ½ scaling with chrominance re-sampling. Filter operation is determined by the CMODE, SCALE, and RESMPL bits of VCxCTL. Table 3-10 shows the input filter mode selection.

  • Page 59: Edge Pixel Replication

    www.ti.com The filtering for the luminance portion of the scaling filter changes depending on if chrominance re-sampling is also enabled. (By changing the luminance filter, the chrominance filters can remain the same.) The resulting values are clamped to between 01h and FEh and sent to the Y, Cb, and Cr capture buffers.

  • Page 60: Ancillary Data Capture

    Ancillary Data Capture Note that edge pixel replication only comes into effect when the full BT.656 stream is being captured. If VCXSTART is greater than 0, then only some of the leading edge replicated pixels are used by the filter. If VCXSTART is greater than m, then none of the leading edge replicated pixels are used.

  • Page 61: Horizontal Ancillary (Hanc) Data Capture

    www.ti.com 3.6.1 Horizontal Ancillary (HANC) Data Capture No special provisions are made for the capture of HANC data. HANC data may be captured using the normal video capture mechanism by programming VCXSTRT to occur before the SAV (when HCOUNT is reset by the EAV code) or by programming VCXSTOP to occur past the EAV code (when HCOUNT is reset by the SAV code).

  • Page 62: Raw Data Fifo Packing

    Raw Data Capture Mode For channel B operation or when the RDFE bit in VCACTL is not set, no field information is available. Some flexibility in capture and DSP notification is still provided in order to accommodate various EDMA structures and processing flows. Each raw data packet is treated similar to a progressive scan video frame.

  • Page 63: Tci Capture Mode

    www.ti.com Figure 3-14. 16-Bit Raw Data FIFO Packing VCLKINA Raw 0 VDIN[19−12] / VDIN[9−2] Raw 11 Raw 7 Raw 3 Raw FIFO TCI Capture Mode The transport channel interface (TCI) capture mode captures MPEG-2 transport data. 3.8.1 TCI Capture Features The video port TCI capture mode supports the following features: Supports SYNC detect using the PACSTRT input from a front-end device.

  • Page 64: Tci Capture Error Detection

    TCI Capture Mode VCLKIN CAPEN É É É PACSTRT É É É VDIN[9:2] É É É Sync Byte Start Capture 3.8.3 TCI Capture Error Detection The video port checks for two types of errors during TCI capture. The first is a packet error on the incoming packet as indicated by an active PACERR signal.

  • Page 65: Tci Data Capture Notification

    www.ti.com counter counts from 0 to 299 at 27 MHz. Each time the 9-bit counter rolls over to 0, the 33-bit counter is incremented by 1. This is equivalent to the PCR timestamp transmitted in the bit-stream. The 33-bit field can also be programmed to count at 27 MHz for compatibility with the MPEG-1 32-bit PCR, by setting the CTMODE bit in VCCTL to 1;...

  • Page 66: Writing To The Fifo

    TCI Capture Mode Table 3-12. TCI Capture Mode Operation (continued) VCACTL Bit FRAME 3.8.6 Writing to the FIFO The captured TCI packet data and the associated time stamps are written into the receive FIFO. The packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and timestamp writes into the FIFO.

  • Page 67: Capture Line Boundary Conditions

    www.ti.com The video port generates a YEVT after the specified number of new samples has been captured in the buffer. The number of samples required to generate YEVT is programmable and is set in the VCTHRLD1 bits of VCATHRLD. VCTHRLD1 should be set to the packet size plus 8 bytes of timestamp. On every YEVT, the EDMA should move data from the buffer to the DSP memory.

  • Page 68: Handling Fifo Overrun In Bt.656 Or Y/C Mode

    Capturing Video in Raw Data Mode number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx, CbEVTx, and CrEVTx are generated by the video capture module. 7. Configure an EDMA channel to move data from YSRCx to a destination in the DSP memory. The channel transfers should be triggered by the YEVTx.

  • Page 69: Handling Fifo Overrun Condition In Raw Data Mode

    www.ti.com 5. Write to VCxTHRLD to set the capture threshold. The threshold needs to be set in units of double word. One double word is equal to 8 bytes. Every time the number of received bytes reaches the number specified by the threshold fields (VCTHRLDx) in the threshold register, a YEVTx is generated by the video capture module.

  • Page 70: Handling Fifo Overrun Condition In Tci Capture Mode

    Video Capture Registers 5. Write to TCISTCMPL, TCISTCMPM, TCISTMSKL, and TCISTMSKM if needed to initiate an interrupt, based on STC absolute time. 6. Write to TCITICKS if an interrupt is desired every x cycles of STC. 7. Write to VPCTL to select TCI capture operation (TCI = 1). 8.

  • Page 71: Video Capture Channel X Status Register (Vcastat, Vcbstat)

    www.ti.com Table 3-13. Video Capture Control Registers (continued) Offset Address Acronym 154h VCBSTOP2 158h VCBVINT 15Ch VCBTHRLD 160h VCBEVTCT 180h TCICTL 184h TCICLKINITL 188h TCICLKINITM 18Ch TCISTCLKL 190h TCISTCLKM 194h TCISTCMPL 198h TCISTCMPM 19Ch TCISTMSKL 1A0h TCISTMSKM 1A4h TCITICKS 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) The video capture channel x status register (VCASTAT, VCBSTAT) indicates the current status of the video capture channel.

  • Page 72: Video Capture Channel A Control Register (Vcactl)

    Video Capture Registers Table 3-14. Video Capture Channel x Status Register (VCxSTAT) Field Descriptions field symval Value FSYNC OF(value) DEFAULT CLEARED FRMC OF(value) DEFAULT NONE CAPTURED CLEAR OF(value) DEFAULT NONE CAPTURED CLEAR OF(value) DEFAULT NONE CAPTURED CLEAR 27-16 VCYPOS OF(value) 0-FFFh DEFAULT 15-13 Reserved -...

  • Page 73: Video Capture Channel A Control Register (Vcactl)

    www.ti.com Figure 3-22. Video Capture Channel A Control Register (VCACTL) RSTCH BLKCAP R/WS-0 R/W-1 Reserved RDFE R/W-0 VCEN Reserved R/W-0 FRAME R/W-0 R/W-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; WS = Write 1 to reset, a write of 0 has no effect; -n = value after reset Table 3-15.
  • Page 74 Video Capture Registers Table 3-15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (continued) field symval OF(value) DEFAULT EAVSAV EXTERN FLDD OF(value) DEFAULT EAVFID VRST OF(value) V1EAV DEFAULT V0EAV HRST OF(value) DEFAULT VCEN OF(value) DEFAULT DISABLE ENABLE 14-13 Reserved LFDE OF(value) DEFAULT...

  • Page 75: Video Capture Channel X Field 1 Start Register (Vcxstrt1)

    www.ti.com Table 3-15. Video Capture Channel A Control Register (VCACTL) Field Descriptions (continued) field symval OF(value) DEFAULT DISABLE ENABLE FRAME OF(value) DEFAULT NONE FRMCAP OF(value) NONE DEFAULT FLDCAP OF(value) NONE DEFAULT FLDCAP Reserved CMODE OF(value) DEFAULT BT656B RAWB RAW16 For complete encoding of these bits, see 3.13.3 Video Capture Channel x Field 1 Start Register (VCxSTRT1) The captured image is a subset of the incoming image.

  • Page 76: Video Capture Channel X Field 1 Stop Register (Vcxstop1)

    Video Capture Registers Figure 3-23. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Reserved Reserved R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-16. Video Capture Channel x Field 1 Start Register (VCxSTRT1) Field Descriptions field symval 31-28 Reserved...

  • Page 77: Video Capture Channel X Field 2 Start Register (Vcxstrt2)

    www.ti.com Figure 3-24. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-17. Video Capture Channel x Field 1 Stop Register (VCxSTOP1) Field Descriptions field symval 31-28 Reserved...

  • Page 78: Video Capture Channel X Field 2 Stop Register (Vcxstop2)

    Video Capture Registers Table 3-18. Video Capture Channel x Field 2 Start Register (VCxSTRT2) Field Descriptions field symval 31-28 Reserved 27-16 VCYSTART OF(value) DEFAULT 15-12 Reserved 11-0 VCXSTART OF(value) DEFAULT For CSL implementation, use the notation VP_VCxSTRT2_field_symval 3.13.6 Video Capture Channel x Field 2 Stop Register (VCxSTOP2) The video capture channel x field 2 stop register (VCxSTOP2) defines the end of the field 2-captured image.

  • Page 79: Video Capture Channel X Vertical Interrupt Register (Vcxvint)

    www.ti.com 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCxVINT) The video capture channel x vertical interrupt register (VCAVINT, VCBVINT) controls the generation of vertical interrupts in each field. In BT.656 or Y/C mode, an interrupt can be generated upon completion of the specified line in a field (end of line when VCOUNT = VINTn).

  • Page 80: Video Capture Channel X Threshold Register (Vcathrld, Vcbthrld)

    Video Capture Registers 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) The video capture channel x threshold register (VCATHRLD, VCBTHRLD) determines when EDMA requests are sent. The VCTHRLD1 bits determine when capture EDMA events are generated. Once the threshold is reached, generation of further EDMA events is disabled until service of the previous event(s) begins (the first FIFO read by the EDMA occurs).

  • Page 81: Video Capture Channel X Event Count Register (Vcxevtct)

    www.ti.com 3.13.9 Video Capture Channel x Event Count Register (VCxEVTCT) The video capture channel x event count register (VCxEVTCT) is programmed with the number of EDMA events to be generated for each capture field. An event counter tracks how many events have been generated and indicates which threshold value (VCTHRLD1 or VCTHRLD2 in VCxTHRLD) to use in event generation and in the outgoing data counter.

  • Page 82: Video Capture Channel B Control Register (Vcbctl)

    Video Capture Registers Figure 3-30. Video Capture Channel B Control Register (VCBCTL) RSTCH BLKCAP R/WS-0 R/W-1 Reserved VCEN Reserved R/W-0 FRAME R/W-0 R/W-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; WS = Write 1 to reset, a write of 0 has no effect; -n = value after reset Table 3-23.
  • Page 83 www.ti.com Table 3-23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (continued) field symval HRST OF(value) DEFAULT VCEN OF(value) DEFAULT DISABLE ENABLE 14-13 Reserved LFDE OF(value) DEFAULT DISABLE ENABLE SFDE OF(value) DEFAULT DISABLE ENABLE RESMPL OF(value) DEFAULT DISABLE ENABLE Reserved SCALE OF(value)

  • Page 84: Tci Capture Control Register (Tcictl)

    Video Capture Registers Table 3-23. Video Capture Channel B Control Register (VCBCTL) Field Descriptions (continued) field symval OF(value) NONE DEFAULT FLDCAP Reserved CMODE OF(value) DEFAULT BT656B RAWB 3.13.11 TCI Capture Control Register (TCICTL) The ERRFILT, STEN, and TCKEN bits may be written at any time. To ensure stable counter operation, writes to the CTMODE bit are disabled unless the system time counter is halted (ENSTC = 0).

  • Page 85: Tci Clock Initialization Lsb Register (Tciclkinitl)

    www.ti.com Table 3-24. TCI Capture Control Register (TCICTL) Field Descriptions (continued) field symval STEN OF(value) DEFAULT DISABLE CTMODE OF(value) DEFAULT 90KHZ STCLK ERRFILT OF(value) DEFAULT ACCEPT REJECT Reserved 3.13.12 TCI Clock Initialization LSB Register (TCICLKINITL) The transport stream interface clock initialization LSB register (TCICLKINITL) is used to initialize the hardware counter to synchronize with the system time clock.

  • Page 86: Tci Clock Initialization Msb Register (Tciclkinitm)

    Video Capture Registers 3.13.13 TCI Clock Initialization MSB Register (TCICLKINITM) The transport stream interface clock initialization MSB register (TCICLKINITM) is used to initialize the hardware counter to synchronize with the system time clock. . On receiving the first packet containing a program clock reference (PCR) header, the DSP writes the most-significant bit (MSB) of the PCR and the 9-bit PCR extension into TCICLKINITM.

  • Page 87: Tci System Time Clock Msb Register (Tcistclkm)

    www.ti.com Figure 3-34. TCI System Time Clock LSB Register (TCISTCLKL) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-27. TCI System Time Clock LSB Register (TCISTCLKL) Field Descriptions field symval 31-0 OF(value) 0-FFFF FFFFh Not used. DEFAULT For CSL implementation, use the notation VP_TCISTCLKL_PCR_symval 3.13.15 TCI System Time Clock MSB Register (TCISTCLKM)

  • Page 88: Tci System Time Clock Compare Lsb Register (Tcistcmpl)

    Video Capture Registers 3.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) The transport stream interface system time clock compare LSB register (TCISTCMPL) is used to generate an interrupt at some absolute time based on the STC. TCISTCMPL holds the 32 least-significant bits (LSBs) of the absolute time compare (ATC).

  • Page 89: Tci System Time Clock Compare Mask Lsb Register (Tcistmskl)

    www.ti.com Table 3-30. TCI System Time Clock Compare MSB Register (TCISTCMPM) Field Descriptions field symval 31-1 Reserved OF(value) DEFAULT For CSL implementation, use the notation VP_TCISTCMPM_ATC_symval 3.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) The transport stream interface system time clock compare mask LSB register (TCISTMSKL) holds the 32 least-significant bits (LSBs) of the absolute time compare mask (ATCM).

  • Page 90: Tci System Time Clock Ticks Interrupt Register (Tciticks)

    Video Capture Registers Figure 3-39. TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-32. TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) Field Descriptions field symval 31-1...

  • Page 91: Video Capture Fifo Registers

    www.ti.com 3.14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers.

  • Page 92: Video Display Port

    The video port peripheral can operate as a video capture port, video display port, or transport stream interface (TCI) capture port. This chapter discusses the video display port. Topic Video Display Mode Selection BT.656 Video Display Mode Y/C Video Display Mode Video Output Filtering Ancillary Data Display Raw Data Display Mode...

  • Page 93: Video Display Mode Selection

    www.ti.com Video Display Mode Selection The video display module operates in one of three modes as listed in the video display control register (VDCTL). The Y/C and 16-bit raw display modes may only be selected if the DCDIS bit in the video port control register (VPCTL) is cleared to 0. DMODE Bits Mode 8-Bit ITU-R BT.656 Display...

  • Page 94: Smpte 296M Compatible Progressive Scan Display

    Video Display Mode Selection Figure 4-2. SMPTE 296M Compatible Progressive Scan Display Field 1 Line 26 Line 27 Line 28 Line 29 Line 30 Line 741 Line 742 Line 743 Line 744 Line 745 Video Display Port www.ti.com SPRUEM1 – May 2007 Submit Documentation Feedback...

  • Page 95: Interlaced Blanking Intervals And Video Areas

    www.ti.com Figure 4-3. Interlaced Blanking Intervals and Video Areas SPRUEM1 – May 2007 Submit Documentation Feedback Field 1 Vertical Blanking Field 1 Image Vertical Offset Field 1 Image Width Field 2 Vertical Blanking Field 2 Image Vertical Offset Field 2 Image Width Video Display Mode Selection Field 1 Active Video Field 2 Active Video...

  • Page 96: Video Display Counters

    Video Display Mode Selection Figure 4-4. Progressive Blanking Intervals and Video Area 4.1.2 Video Display Counters To generate the image timing, the video display module uses five counters: Frame line counter (FLCOUNT) Frame pixel counter (FPCOUNT) Image line counter (ILCOUNT) Image pixel counter (IPCOUNT) Video clock counter (VCCOUNT) The frame line counter (FLCOUNT) counts the total number of lines per frame including vertical blanking...

  • Page 97: Horizontal Blanking And Horizontal Sync Timing

    www.ti.com Figure 4-5 shows how the horizontal blanking and horizontal synchronization signals are triggered. (HBLNK and HSYNC are shown active high). Figure 4-5. Horizontal Blanking and Horizontal Sync Timing 719 720 FPCOUNT HBLNK HSYNC FPCOUNT = HBLNKSTART The 12-bit FLCOUNT counts which scan line is being generated. The FLCOUNT is reset to 1 after reaching the count specified in VDFRMSZ.

  • Page 98: Sync Signal Generation

    BT.656 Video Display Mode 4.1.3 Sync Signal Generation The video display module must generate a number of control signals for both internal and external use. As seen in Section 4.1.2, the HSYNC, HBLNK, VSYNC, VBLNK, and FLD signals are generated directly from the pixel and line counters and comparison registers.

  • Page 99: Display Timing Reference Codes

    www.ti.com 4.2.1 Display Timing Reference Codes The end active video (EAV) code and start active video (SAV) code are issued at the start of each video line. EAV and SAV codes have a fixed format. The format is shown in codes define the end and start of the horizontal-blanking interval, respectively, and they also indicate the current field number and the vertical blanking interval.

  • Page 100: Digital Vertical F And V Transitions

    BT.656 Video Display Mode SAV and EAV codes are identified by a 3-byte preamble of FFh, 00h, and 00h. This combination must be avoided in the video data output by the video port to prevent accidental generation of an invalid sync code.

  • Page 101: Blanking Codes

    www.ti.com 4.2.2 Blanking Codes The time between the EAV and SAV code on each line represents the horizontal blanking interval. During this time, the video port outputs digital video blanking values. These values are 10.0h for luma (Y) samples and 80.0h for chroma (Cb/Cr) samples. These values are also output during the active line period of vertical blanking (between SAV and EAV when V = 1).

  • Page 102: Y/C Video Display Mode

    Y/C Video Display Mode Y/C Video Display Mode The Y/C display mode is similar to the BT.656 display mode but outputs 8-bit data on separate luma and chroma data streams. One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co-sited with every other luminance sample.

  • Page 103: Y/C Fifo Unpacking

    www.ti.com 4.3.4 Y/C FIFO Unpacking Display data is always packed into the FIFOs in 64-bit words and must be unpacked before being sent to the display data pipeline. By default, data is unpacked from right to left. The 8-bit Y/C mode uses three FIFOs for color separation. Samples are unpacked as shown in Figure 4-14.

  • Page 104: Chrominance Re-Sampling Operation

    Video Output Filtering 4.4.2 Chrominance Re-sampling Operation Chrominance re-sampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples. This filter performs the conversion between interspersed YCbCr 4:2:2 format and co-sited YCbCr 4:2:2 format. The vertical portion of the conversion from YCbCr 4:2:0 to interspersed YCbCr 4:2:2 must be performed in software.

  • Page 105: Edge Pixel Replication

    www.ti.com YCbCr 4:2:2 interspersed source pixels 2x upscaled YCbCr 4:2:2 co-sited output Y’ Cb’ = (-3Cb + 101Cb + 33Cb Cr’ = (-3Cr + 101Cr + 33Cr Luma (Y) sample 4.4.4 Edge Pixel Replication Because four tap filters are used on the output, the first and last two pixels on each line must be mirrored. An example of how the filter uses the mirrored pixels for the luminance filter (2x co-sited) is shown in Figure 4-18.

  • Page 106: Ancillary Data Display

    Ancillary Data Display Figure 4-20. Interspersed Chroma Edge Replication Leading edge replicated chroma samples Cb’ = (-3Cb + 33Cb + 101Cb -3Cb )/128 Cr’ = (-3Cr + 33Cr + 101Cr -3Cr )/128 Cb’ = (-3Cb + 101Cb + 33Cb Cr’ = (-3Cr + 101Cr + 33Cr...

  • Page 107: Raw Mode Rgb Output Support

    www.ti.com 4.6.1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set. FPCOUNT increments only when INCPIX samples have been sent out. This option allows proper tracking of the display pixels when sending out sequential RGB samples.

  • Page 108: Video Display Field And Frame Operation

    Video Display Field and Frame Operation Video Display Field and Frame Operation As a video source, the video port always outputs entire frames of data and transmits continuous video control signals. Depending on the EDMA structure, however, the video port may need to interrupt the DSP on a field or frame basis to allow it to update video port registers or EDMA parameters.

  • Page 109: Video Display Event Generation

    www.ti.com VDCTL Bit FRAME 4.7.2 Video Display Event Generation The display FIFOs are filled using EDMAs as requested by the video port EDMA events. The VDTHRLD value indicates the level at which the FIFO has enough room to receive another EDMA block of data. Depending on the size of the EDMA, the FIFO may have room for multiple transfers before reaching the VDTHRLD level.

  • Page 110: Display Timing Examples

    Display Timing Examples Figure 4-24. Display Line Boundary Example VCLKOUT VDOUT[9−2] VDOUT[19−12] 5655 4847 Y 71 Y 70 Y FIFO 5655 4847 Cb 7 Cb 6 Cb 38 Cb FIFO 5655 4847 Cr 7 Cr 6 Cr 38 Cr FIFO Display Timing Examples The following are examples of display output for several modes of operation.

  • Page 111: Bt.656 Interlaced Display Horizontal Timing Example

    www.ti.com Figure 4-25. BT.656 Interlaced Display Horizontal Timing Example VCLKIN FPCOUNT 720 721 722 723 IPCOUNT 703 703 703 703 )(A)(C) VCTL1 (HBLNK (A)(C) VCTL1 (HSYNC) VCLKOUT VDOUT[9−2] EAV Blanking Data FLCOUNT n − 1 FRMWIDTH = 858 IMGHOFF1 = 8 HBLNKSTART = 720 IMGHSIZE1 = 704 HBLNKSTOP = 856...
  • Page 112 Display Timing Examples The interlaced BT.656 vertical output timing is shown in high and active field 2 is 243-lines high. This example shows the 480-line image window centered in the screen. This results in an IMGVOFFn of 3 lines and also results in a non-data line at the end of field 1 due to its extra active line.

  • Page 113: Interlaced Raw Display Example

    www.ti.com Figure 4-26. BT.656 Interlaced Display Vertical Timing Example FLCOUNT Field 1 blanking Field 1 active Field 1 image Field 2 blanking Field 2 active Field 2 image IMGVOFF1 = 3 IMGVSIZE1 = 240 IMGVOFF2 = 3 IMGVSIZE2 = 240 FRMHEIGHT = 525 VBITSET1 = 1 VBITCLR1 = 20...

  • Page 114: Raw Interlaced Display Horizontal Timing Example

    Display Timing Examples Figure 4-27. Raw Interlaced Display Horizontal Timing Example VCLKIN FPCOUNT IPCOUNT (A)(B) VCTL1 (HBLNK) (A)(B) VCTL1 (HSYNC) VCLKOUT É É É É É É É É É ](B) VDOUT[19−2 É É É É É É FLCOUNT n − 1 FRMWIDTH = 858 IMGHOFF1 = 8 HBLNKSTART = 720...

  • Page 115: Raw Interlaced Display Vertical Timing Example

    www.ti.com The vertical output timing for raw mode is shown in window. Note that the raw display mode is typically noninterlaced for output to a monitor. This example shows the more complex interlaced case. The active field 1 is 242.5-lines high and active field 2 is 242.5-lines high.

  • Page 116: Y/C Progressive Display Example

    Display Timing Examples 4.9.3 Y/C Progressive Display Example This section shows an example of progressive display operation. The output format follows SMPTE 296M-2001 specifications for a 1280 x 720/60 system. The example is for a 1264 x 716 progressive output image.

  • Page 117: Y/C Progressive Display Horizontal Timing Example

    www.ti.com Figure 4-29. Y/C Progressive Display Horizontal Timing Example VCLKIN FPCOUNT IPCOUNT (A)(C) VCTL1 (HBLNK) (A)(C) VCTL1 (HSYNC) VCLKOUT VDOUT[9−2] VDOUT[19−2] Blanking Data FLCOUNT n − 1 FRMWIDTH = 1650 IMGHOFF1 = 8 HBLNKSTART = 1280 IMGHSIZE1 = 1264 HBLNKSTOP = 1646 MGHOFF2 = n/a IMGHSIZE2 = n/a Assumes VCT0P bit in VPCTL is set to 1 (active-low output).

  • Page 118: Y/C Progressive Display Vertical Timing Example

    Display Timing Examples The vertical output timing is shown in 720-lines high. This example shows the 716-line image window with an IMGVOFFn of 3 lines and also results in a non-data line at the end of the field. The VBLNK and VSYNC signals are shown as they would be output for active-low operation. Note that only one of the two signals is actually available externally.

  • Page 119: Displaying Video In Bt.656 Or Y/C Mode

    www.ti.com 4.10 Displaying Video in BT.656 or Y/C Mode In order to display video in the BT.656 or Y/C format, the following steps are needed: 1. To use the desired Video Port, program the Pin Mux Register (PINMUX) appropriately to ensure that the multiplexed pins work as Video Port Pins.

  • Page 120: Displaying Video In Raw Data Mode

    Displaying Video in Raw Data Mode 22. Wait for 2 or more frame times, to allow the display counters and control signals to become properly synchronized. 23. Write to VDCTL to clear the BLKDIS bit. 24. Display is enabled at the start of the first frame after BLKDIS = 0 and begins with the first selected field.

  • Page 121: Handling Under-Run Condition Of The Display Fifo

    www.ti.com by total double words per Y EDMA. 20. Write to VPIE to enable under-run (DUND) and display complete (DCMP) interrupts, if desired. 21. Write to VDTHRLD to set the display FIFO threshold (VDTHRLD bits) and the FPCOUNT increment rate (INCPIX bit). 22.

  • Page 122: Video Display Registers

    Video Display Registers 4.12 Video Display Registers The registers for controlling the video display mode of operation are listed in device-specific datasheet for the memory address of these registers. Offset Address Acronym 200h VDSTAT 204h VDCTL 208h VDFRMSZ 20Ch VDHBLNK 210h VDVBLKS1 214h...

  • Page 123: Video Display Control Register (Vdctl)

    www.ti.com Figure 4-31. Video Display Status Register (VDSTAT) Reserved FRMD R/WC-0 R/WC-0 R/WC-0 Reserved VBLNK VDFLD LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-6. Video Display Status Register (VDSTAT) Field Descriptions field symval Reserved FRMD OF(value)

  • Page 124: Video Display Control Register (Vdctl)

    Video Display Registers The video display is controlled by the video display control register (VDCTL). The video display control register (VDCTL) is shown in Figure 4-32. Video Display Control Register (VDCTL) RSTCH BLKDIS Reserved R/WS-0 R/W-1 R/W-0 R/W-0 R/W-0 VDEN Reserved RGBX R/W-0...
  • Page 125 www.ti.com Table 4-7. Video Display Control Register (VDCTL) Field Descriptions (continued) field symval OF(value) DEFAULT OUTPUT FSINPUT OF(value) DEFAULT OUTPUT VSINPUT OF(value) DEFAULT OUTPUT HSINPUT VCTL3S OF(value) DEFAULT CBLNK 19-18 VCTL2S OF(value) DEFAULT VYSYNC VBLNK CSYNC 17-16 VCTL1S OF(value) DEFAULT HYSYNC HBLNK AVID...
  • Page 126 Video Display Registers Table 4-7. Video Display Control Register (VDCTL) Field Descriptions (continued) field symval DVEN OF(value) DEFAULT BLANKING RESMPL OF(value) DEFAULT DISABLE ENABLE Reserved SCALE OF(value) DEFAULT NONE OF(value) DEFAULT DISABLE ENABLE FRAME OF(value) DEFAULT NONE FRMDIS OF(value) DEFAULT NONE FLDDIS OF(value)

  • Page 127: Video Display Frame Size Register (Vdfrmsz)

    www.ti.com 4.12.3 Video Display Frame Size Register (VDFRMSZ) The video display frame size register (VDFRMSZ) sets the display channel frame size by setting the ending values for the frame line counter (FLCOUNT) and the frame pixel counter (FPCOUNT). The FPCOUNT starts at 0 and counts to FRMWIDTH - 1 before restarting. The FLCOUNT starts at 1 and counts to FRMHEIGHT before restarting.

  • Page 128: Video Display Field 1 Vertical Blanking Start Register (Vdvblks1)

    Video Display Registers Figure 4-34. Video Display Horizontal Blanking Register (VDHBLNK) Reserved HBDLA Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-9. Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions field symval 31-28 Reserved 27-16 HBLNKSTOP OF(value)

  • Page 129: Video Display Field 1 Vertical Blanking End Register (Vdvblke1)

    www.ti.com Figure 4-35. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-10. Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Descriptions field symval 31-28 Reserved...

  • Page 130: Video Display Field 2 Vertical Blanking Start Register (Vdvblks2)

    Video Display Registers Table 4-11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions field symval 31-28 Reserved 27-16 VBLNKYSTOP1 OF(value) DEFAULT 15-12 Reserved 11-0 VBLNKXSTOP1 OF(value) DEFAULT For CSL implementation, use the notation VP_VDVBLKE1_field_symval 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) The video display field 2 vertical blanking start register (VDVBLKS2) controls the start of vertical blanking in field 2.

  • Page 131: Video Display Field 2 Vertical Blanking End Register (Vdvblke2)

    www.ti.com Table 4-12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions field symval 11-0 VBLNKXSTART2 OF(value) DEFAULT 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) The video display field 2 vertical blanking end register (VDVBLKE2) controls the end of vertical blanking in field 2.

  • Page 132: Video Display Field 1 Image Offset Register (Vdimgoff1)

    Video Display Registers 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) The video display field 1 image offset register (VDIMGOFF1) defines the field 1 image offset and specifies the starting location of the displayed image relative to the start of the active display. The image line counter (ILCOUNT) is reset to 1 on the first image line (when FLCOUNT = VBLNKYSTOP1 + IMGVOFF1).

  • Page 133: Video Display Field 1 Image Size Register (Vdimgsz1)

    www.ti.com Table 4-14. Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions (continued) field symval 11-0 IMGHOFF1 OF(value) DEFAULT 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) The video display field 1 image size register (VDIMGSZ1) defines the field 1 image area and specifies the size of the displayed image within the active display.

  • Page 134: Video Display Field 2 Image Offset Register (Vdimgoff2)

    Video Display Registers 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) The video display field 2 image offset register (VDIMGOFF2) defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display. The image line counter (ILCOUNT) is reset to 1 on the first image line (when FLCOUNT = VBLNKYSTOP2 + IMGVOFF2).

  • Page 135: Video Display Field 2 Image Size Register (Vdimgsz2)

    www.ti.com 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) The video display field 2 image size register (VDIMGSZ2) defines the field 2 image area and specifies the size of the displayed image within the active display. The image pixel counter (IPCOUNT) counts displayed image pixel output on each of the displayed image. Displayed image pixel output stops when IPCOUNT = IMGHSIZE2.

  • Page 136: Video Display Field 2 Timing Register (Vdfldt2)

    Video Display Registers Figure 4-43. Video Display Field 1 Timing Register (VDFLDT1) Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-18. Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions field symval 31-28 Reserved 27-16 FLD1YSTART OF(value)

  • Page 137: Video Display Threshold Register (Vdthrld)

    www.ti.com Table 4-19. Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions (continued) field symval 11-0 FLD2XSTART OF(value) DEFAULT 4.12.15 Video Display Threshold Register (VDTHRLD) The video display threshold register (VDTHRLD) sets the display FIFO threshold to determine when to load more display data.

  • Page 138: Video Display Horizontal Synchronization Register (Vdhsync)

    Video Display Registers Table 4-20. Video Display Threshold Register (VDTHRLD) Field Descriptions (continued) field symval 11-10 Reserved VDTHRLD1 OF(value) DEFAULT 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) The video display horizontal synchronization register (VDHSYNC) controls the timing of the horizontal synchronization signal.

  • Page 139: Video Display Field 1 Vertical Synchronization End Register (Vdvsyne1)

    www.ti.com The video display field 1 vertical synchronization start register (VDVSYNS1) is shown in described in Table 4-22. Figure 4-47. Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-22.

  • Page 140: Video Display Field 2 Vertical Synchronization Start Register (Vdvsyns2)

    Video Display Registers Table 4-23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Field Descriptions field symval 15-12 Reserved 11-0 VSYNCXSTOP1 OF(value) DEFAULT 4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) The video display field 2 vertical synchronization start register (VDVSYNS2) controls the start of vertical synchronization in field 2.

  • Page 141: Video Display Counter Reload Register (Vdreload)

    www.ti.com Figure 4-50. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-25. Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Field field symval 31-28 Reserved 27-16 VSYNCYSTOP2...

  • Page 142: Video Display Event Register (Vddispevt)

    Video Display Registers 4.12.22 Video Display Event Register (VDDISPEVT) The video display event register (VDDISPEVT) is programmed with the number of EDMA events to be generated for display field 1 and field 2. The video display event register (VDDISPEVET) is shown in Figure 4-52.

  • Page 143: Video Display Default Display Value Register (Vddefval)

    www.ti.com Figure 4-53. Video Display Clipping Register (VDCLIP) CLIPCHIGH R/W-1111-0000 CLIPYHIGH R/W-1110-1011 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-28. Video Display Clipping Register (VDCLIP) Field Descriptions field symval 31-24 CLIPCHIGH OF(value) DEFAULT 23-16 CLIPCLOW OF(value) DEFAULT...

  • Page 144: Video Display Vertical Interrupt Register (Vdvint)

    Video Display Registers Figure 4-54. Video Display Default Display Value Register (VDDEFVAL) CRDEFVAL R/W-0 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 4-55. Video Display Default Display Value Register (VDDEFVAL) - Raw Data Mode LEGEND: R/W = Read/Write;...

  • Page 145: Video Display Field Bit Register (Vdfbit)

    www.ti.com Figure 4-56. Video Display Vertical Interrupt Register (VDVINT) VIF2 Reserved R/W-0 VIF1 Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-30. Video Display Vertical Interrupt Register (VDVINT) Field Descriptions field symval VIF2 OF(value) DEFAULT...

  • Page 146: Video Display Field 1 Vertical Blanking Bit Register (Vdvbit1)

    Video Display Registers Figure 4-57. Video Display Field Bit Register (VDFBIT) Reserved Reserved LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 4-31. Video Display Field Bit Register (VDFBIT) Field Descriptions field symval 31-28 Reserved 27-16 FBITSET OF(value) DEFAULT...

  • Page 147: Video Display Field 2 Vertical Blanking Bit Register (Vdvbit2)

    www.ti.com Table 4-32. Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions field symval 31-28 Reserved 27-16 VBITCLR1 OF(value) DEFAULT 15-12 Reserved 11-0 VBITSET1 OF(value) DEFAULT For CSL implementation, use the notation VP_VDVBIT1_field_symval 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) The video display field 2 vertical blanking bit register (VDVBIT2) controls the V bit in the EAV and SAV timing control words for field 2.

  • Page 148: Video Display Registers Recommended Values

    Video Display Registers Recommended Values Table 4-33. Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions (continued) field symval 11-0 VBITSET2 OF(value) DEFAULT 4.13 Video Display Registers Recommended Values Sample recommended values (decimal) for video display registers for BT.656 output are given in Table 4-34.

  • Page 149: Video Display Fifo Registers

    www.ti.com 4.14 Video Display FIFO Registers The display FIFO mapping registers are listed in to the display FIFOs. These pseudo-registers should be mapped into DSP memory space rather than configuration register space in order to provide high-speed access. See the device-specific datasheet for the memory address of these registers.

  • Page 150: General-Purpose I/O Operation

    SPRUEM1 – May 2007 General-Purpose I/O Operation Signals not used for video display or video capture can be used as general-purpose input/output (GPIO) signals. Topic Page GPIO Registers General-Purpose I/O Operation SPRUEM1 – May 2007 Submit Documentation Feedback...

  • Page 151: Gpio Registers

    www.ti.com GPIO Registers The GPIO register set includes required registers such as peripheral identification and emulation control. The GPIO registers are listed in these registers. Offset Address Acronym VPPID PFUNC PDIR PDIN PDOUT PDSET PDCLR PIEN PIPOL PISTAT PICLR The absolute address of the registers is device/port specific and is equal to the base address + offset address. See the device-specific datasheet to verify the register addresses.

  • Page 152: Video Port Peripheral Identification Register (Vppid)

    GPIO Registers 5.1.1 Video Port Peripheral Identification Register (VPPID) The video port peripheral identification register (VPPID) is a read-only register used to store information about the peripheral. The video port peripheral identification register (VPPID) is shown in Figure 5-1. Video Port Peripheral Identification Register (VPPID) Reserved CLASS R-0000 1001...

  • Page 153: Video Port Peripheral Control Register (Pcr)

    www.ti.com 5.1.2 Video Port Peripheral Control Register (PCR) The video port peripheral control register (PCR) determines operation during emulation. Normal operation is to not halt the port during emulation suspend. This allows a displayed image to remain visible during suspend. However, this will only work if one of the continuous capture/display modes is selected because non-continuous modes require CPU intervention for EDMAs to continue indefinitely (and the CPU is halted during emulation suspend).

  • Page 154: Video Port Pin Function Register (Pfunc)

    GPIO Registers 5.1.3 Video Port Pin Function Register (PFUNC) The video port pin function register (PFUNC) selects the video port pins as GPIO. Each bit controls either one pin or a set of pins. When a bit is set to 1, it enables the pin(s) that map to it as GPIO. The GPIO feature should not be used for pins that are used as part of the capture or display operation.
  • Page 155 www.ti.com Table 5-4. Video Port Pin Function Register (PFUNC) Field Descriptions (continued) field symval PFUNC10 OF(value) DEFAULT NORMAL VDATA10TO19 Reserved PFUNC0 OF(value) DEFAULT NORMAL VDATA0TO9 SPRUEM1 – May 2007 Submit Documentation Feedback Value Description PFUNC10 bit determines if VDATA[19-12] pins function as GPIO. Pins function normally.

  • Page 156: Video Port Pin Direction Register (Pdir)

    GPIO Registers 5.1.4 Video Port Pin Direction Register (PDIR) The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC. If a bit is set to 1, the relevant pin or pin group acts as an output. If a bit is cleared to 0, the pin or pin group functions as an input.
  • Page 157 www.ti.com Table 5-5. Video Port Pin Direction Register (PDIR) Field Descriptions (continued) field symval PDIR12 OF(value) DEFAULT VDATA12TO15IN VDATA12TO15OUT 11-9 Reserved PDIR8 OF(value) DEFAULT VDATA8TO9IN VDATA8TO9OUT Reserved PDIR4 OF(value) DEFAULT VDATA4TO7IN VDATA4TO7OUT Reserved PDIR0 OF(value) DEFAULT VDATA0T32IN VDATA0T32OUT SPRUEM1 – May 2007 Submit Documentation Feedback Value Description PDIR12 bit controls the direction of the VDATA[15–12] pins.

  • Page 158: Video Port Pin Data Input Register (Pdin)

    GPIO Registers 5.1.5 Video Port Pin Data Input Register (PDIN) PDIN reflects the state of the video port pins. When read, PDIN returns the value from the pin's input buffer (with appropriate synchronization) regardless of the state of the corresponding PFUNC or PDIR bit. The read-only video port pin data input register (PDIN) is shown in Figure 5-5.

  • Page 159: Video Port Pin Data Output Register (Pdout)

    www.ti.com 5.1.6 Video Port Pin Data Output Register (PDOUT) The bits of PDOUT determine the value driven on the corresponding GPIO pin, if the pin is configured as an output. Writes do not affect pins not configured as GPIO outputs. The bits in PDOUT are set or cleared by writing to this register directly.
  • Page 160 GPIO Registers Table 5-7. Video Port Pin Data Out Register (PDOUT) Field Descriptions (continued) field symval PDOUT20 OF(value) DEFAULT VCTL1LO VCTL1HI 19-2 PDOUT[19-2] OF(value) DEFAULT VDATAnLO VDATAnHI General-Purpose I/O Operation Value Description PDOUT20 bit drives the VCTL1 pin only when the GPIO is configured as output. When reading data, returns the bit value in PDOUT20, does not return input from pin.

  • Page 161: Video Port Pin Data Set Register (Pdset)

    www.ti.com 5.1.7 Video Port Pin Data Set Register (PDSET) PDSET is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs high. Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT.

  • Page 162: Video Port Pin Data Clear Register (Pdclr)

    GPIO Registers 5.1.8 Video Port Pin Data Clear Register (PDCLR) PDCLR is an alias of the video port pin data output register (PDOUT) for writes only and provides an alternate means of driving GPIO outputs low. Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT.

  • Page 163: Video Port Pin Interrupt Enable Register (Pien)

    www.ti.com 5.1.9 Video Port Pin Interrupt Enable Register (PIEN) The GPIOs can be used to generate DSP interrupts or EDMA events. The PIEN selects which pins may be used to generate an interrupt. Only pins whose corresponding bits in PIEN are set may cause their corresponding PISTAT bit to be set.

  • Page 164: Video Port Pin Interrupt Polarity Register (Pipol)

    GPIO Registers 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) The PIPOL determines the GPIO pin signal polarity that generates an interrupt. The video port pin interrupt polarity register (PIPOL) is shown in Figure 5-10. Video Port Pin Interrupt Polarity Register (PIPOL) Reserved PIPOL22 PIPOL21...

  • Page 165: Video Port Pin Interrupt Status Register (Pistat)

    www.ti.com 5.1.11 Video Port Pin Interrupt Status Register (PISTAT) PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt. A bit in PISTAT is set when the corresponding GPIO pin is configured as an interrupt (the corresponding bit in PIEN is set, the pin is enabled for GPIO in PFUNC, and the pin is configured as an input in PDIR) and the appropriate transition (as selected by the corresponding PIPOL bit) occurs on the pin.

  • Page 166: Video Port Pin Interrupt Clear Register (Piclr)

    GPIO Registers 5.1.12 Video Port Pin Interrupt Clear Register (PICLR) PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bit of PICLR clears the corresponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s. The video port pin interrupt clear register (PICLR) is shown in Figure 5-12.

  • Page 167: Vcxo Interpolated Control Port

    This chapter provides an overview of the VCXO interpolated control (VIC) port. Topic Overview Interface Operational Details Enabling VIC Port VIC Port Registers SPRUEM1 – May 2007 Submit Documentation Feedback VCXO Interpolated Control Port SPRUEM1 – May 2007 Page VCXO Interpolated Control Port...

  • Page 168: Overview

    Overview Overview The VCXO interpolated control (VIC) port provides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. The frequency of interpolation is dependent on the resolution needed. When the video port is used in transport stream interface (TCI) mode, the VIC port is used to control the system clock, VCXO, for MPEG transport stream The VIC port supports following features: Single-bit interpolated VCXO control...

  • Page 169: Operational Details

    www.ti.com Operational Details Synchronization is an important aspect of decoding and presenting data in real-time digital data delivery systems. This is addressed in the MPEG transport packets by transmitting timing information in the adaptation fields of selected data packets. This serves as a reference for timing comparison in the receiving system.

  • Page 170: Enabling Vic Port

    Enabling VIC Port Enabling VIC Port Perform the following steps to enable the VIC port. 1. Clear the GO bit in the VIC control register (VICCTL) to 0. 2. Set the PRECISION bits in VICCTL to the desired precision. 3. Set the VIC clock divider register (VICDIV) bits to appropriate value based on the precision and interpolation frequency.

  • Page 171: Vic Control Register (Vicctl)

    www.ti.com 6.5.1 VIC Control Register (VICCTL) The VIC control register (VICCTL) is shown in LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-4. VIC Control Register (VICCTL) Field Descriptions field symval 31-4 Reserved PRECISION OF(value) DEFAULT 16BITS...

  • Page 172: Vic Input Register (Vicin)

    VIC Port Registers 6.5.2 VIC Input Register (VICIN) The DSP writes the input bits for VCXO interpolated control in the VIC input register (VICIN). The DSP decides how often to update VICIN. The DSP can write to VICIN only when the GO bit in the VIC control register (VICCTL) is set to 1.

  • Page 173: Vic Clock Divider Register (Vicdiv)

    www.ti.com 6.5.3 VIC Clock Divider Register (VICDIV) The VIC clock divider register (VICDIV) defines the clock divider for the VIC interpolation frequency. The VIC interpolation frequency is obtained by dividing the module clock. The divider value written to VICDIV Divider + Round DCLK R ] where DCLK is the CPU clock divided by 2, and R is the desired interpolation frequency.

  • Page 174: Important Notice

    TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Amplifiers amplifier.ti.com...

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