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VCLKIN
FPCOUNT
IPCOUNT
(A)(C)
VCTL1 (HBLNK)
(A)(C)
VCTL1 (HSYNC)
VCLKOUT
(C)
VDOUT[9−2]
(C)
VDOUT[19−2]
FLCOUNT
n − 1
FRMWIDTH = 1650
HBLNKSTART = 1280
HBLNKSTOP = 1646
A
Assumes VCT0P bit in VPCTL is set to 1 (active-low output). HSYNC output when VCTL1S bit in VDCTL is set to 00, HBLNK output when VCTL1S bit is set 01.
B
HBLNK operation when HBDLA bit in VDHBLNK is set to 1.
C
Diagram assumes a two VCLK pipeline delay between internal counters and output signals.
SPRUEM1 – May 2007
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Figure 4-29. Y/C Progressive Display Horizontal Timing Example
4
362
Blanking
EAV
Blanking Data
IMGHOFF1 = 8
HSYNCSTART = 1350
IMGHSIZE1 = 1264
HSYNCSTOP = 1430
MGHOFF2 = n/a
IMGHSIZE2 = n/a
4
1280
One Line
(B)
Display Image
É
Active Video
É É
É
É
SAV
n
Display Timing Examples
Next
Line
EAV
n + 1
Video Display Port
117
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