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3.14 Video Capture FIFO Registers
The capture FIFO mapping registers are listed in
capture FIFOs. These pseudo-registers should be mapped into DSP memory space rather than
configuration register space in order to provide high-speed access. See the device-specific datasheet for
the memory address of these registers. The function of the video capture FIFO mapping registers is listed
in
Table
3-35.
Offset Address
00h
20h
40h
00h
20h
40h
(1)
The absolute address of the registers is device/port specific and is equal to the FIFO base address
+ offset address. See the device-specific datasheet to verify the register addresses.
Register
BT.656 or Y/C
YSRCx
Maps Y capture buffer into DSP
memory.
CBSRCx
Maps Cb capture buffer into DSP
memory.
CRSRCx
Maps Cr capture buffer into DSP
memory.
In BT.656 or Y/C capture mode, three EDMAs move data from the Y, Cb, and Cr capture FIFOs to the
DSP memory by using the memory-mapped YSRCx, CBSRCx, and CRSRCx registers. The EDMA
transfers are triggered by the YEVT, CbEVT, and CrEVT events, respectively.
In raw capture mode, one EDMA channel moves data from the Y capture FIFO to the DSP memory by
using the memory-mapped YSRCx register. The EDMA transfers are triggered by a YEVT event.
The video port packs receive data into 64-bit words in the FIFO and the EDMA should always move
64-bit-wide data from YSRCx, CBSRCx, and CRSRCx to the memory.
SPRUEM1 – May 2007
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Table 3-34. Video Capture FIFO Registers
(1)
Acronym
Register Name
YSRCA
Y FIFO Source Register A
CBSRCA
Cb FIFO Source Register A
CRSRCA
Cr FIFO Source Register A
YSRCB
Y FIFO Source Register B
CBSRCB
Cb FIFO Source Register B
CRSRCB
Cr FIFO Source Register B
Table 3-35. Video Capture FIFO Registers Function
Raw Data
Maps data capture buffer into the
DSP memory.
Not used.
Not used.
Table
3-34. These registers provide read access to the
Capture Mode
Video Capture FIFO Registers
TCI
Maps data capture buffer into the
DSP memory.
Not used.
Not used.
Video Capture Port
91