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2.4.1 Video Port Control Register (VPCTL)
The video port control register (VPCTL) determines the basic operation of the video port.
Not all combinations of the port control bits are unique. The control bit encoding is shown in
Additional mode options are selected using the video capture channel A control register (VCACTL) and
video display control register (VDCTL).
The video port control register (VPCTL) is shown in
31
15
14
VPRST
VPHLT
R/WS-0
R/WC-1
7
6
VCLK2P
VCT3P
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; WC = Write a 1 to clear; WS = Write 1 to set, a write of 0 has no effect; -n = value after reset
Table 2-2. Video Port Control Register (VPCTL) Field Descriptions
(1)
Bit
field
symval
31-16 Reserved
-
15
VPRST
OF(value)
DEFAULT
NO
RESET
14
VPHLT
OF(value)
NONE
DEFAULT
CLEAR
13-6
Reserved
-
7
VCLK2P
OF(value)
DEFAULT
NONE
REVERSE
6
VCT3P
OF(value)
DEFAULT
NONE
ACTIVELOW
(1)
For CSL implementation, use the notation VP_VPCTL_field_symval
SPRUEM1 – May 2007
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Figure 2-1. Video Port Control Register (VPCTL)
Reserved
13
5
4
VCT2P
VCT1P
R/W-0
R/W-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Video port software reset enable bit. VPRST is set by writing a 1. Writing 0 has no
effect.
0
No effect.
1
Flush all FIFOs and set all port registers to their initial values. VCLK1 and VCLK2 are
configured as inputs and all VDATA and VCTL pins are placed in high impedance.
Auto-cleared after reset is complete.
The VPRST bit may take several clock cycles to clear to 0. The VPRST bit should be
polled to make sure the bit is cleared prior to writing to the video port registers.
Video port halt bit. This bit is set upon hardware or software reset. The other VPCTL
bits (except VPRST) can only be changed when VPHLT is 1. VPHLT is cleared by
writing a 1. Writing 0 has no effect.
0
No effect.
1
VPHLT is cleared.
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
VCLK2 pin polarity bit. Has no effect in capture mode.
0
1
Inverts the VCLK2 output clock polarity in display mode.
VCTL3 pin polarity. Does not affect GPIO operation. If VCTL3 pin is used as a FLD
input on the video capture side, then the VCTL3 polarity is not considered; the field
inverse is controlled by the FINV bit in the video capture channel x control register
(VCxCTL).
0
Indicates the VCTL3 control signal (input or output) is active high.
1
Indicates the VCTL3 control signal (input or output) is active low.
Figure 2-1
and described in
R-0
Reserved
R-0
3
2
Reserved
TCI
R-0
R/W-0
Video Port Control Registers
Table
2-3.
Table
2-2.
16
8
1
0
DISP
DCHNL
R/W-0
R/W-0
Video Port
35
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