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TMS320DM647
Texas Instruments TMS320DM647 Manuals
Manuals and User Guides for Texas Instruments TMS320DM647. We have
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Texas Instruments TMS320DM647 manuals available for free PDF download: User Manual
Texas Instruments TMS320DM647 User Manual (174 pages)
Video Port/VCXO Interpolated Control (VIC) Port
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.65 MB
Table of Contents
Table of Contents
3
Preface
13
Overview
16
Video Port
17
Video Port Block Diagram
18
Video Port FIFO
19
EDMA Interface
19
Video Capture FIFO Configurations
20
BT.656 Video Capture FIFO Configuration
20
Bit Raw Video Capture and TCI Video Capture FIFO Configuration
21
Y/C Video Capture FIFO Configuration
22
Video Display FIFO Configurations
23
Bit Raw Video Capture FIFO Configuration
23
BT.656 Video Display FIFO Configuration
23
Bit Raw Video Display FIFO Configuration
23
Bit Locked Raw Video Display FIFO Configuration
24
Bit Raw Video Display FIFO Configuration
24
Video Port Registers
25
Y/C Video Display FIFO Configuration
25
Video Port Pin Mapping
26
Video Capture Signal Mapping
26
Video Display Signal Mapping
26
VDIN Bus Usage for Capture Modes
27
VDIN Data Bus Usage for Capture Modes
27
VDOUT Data Bus Usage for Display Modes
28
Video Port Pin Multiplexing
28
Videoport Clocking
28
Video Port
29
Reset Operation
30
Power-On Reset
30
Peripheral Bus Reset
30
Software Port Reset
30
Capture Channel Reset
31
Display Channel Reset
31
Interrupt Operation
31
EDMA Operation
32
Capture EDMA Event Generation
32
Display EDMA Event Generation
33
EDMA Size and Threshold Restrictions
33
EDMA Interface Operation
34
Video Port Control Registers
34
Video Port Control Register (VPCTL)
35
Video Port Control Register (VPCTL) Field Descriptions
35
Video Port Operating Mode Selection
36
Video Port Status Register (VPSTAT)
37
Video Port Status Register (VPSTAT) Field Descriptions
37
Video Port Interrupt Enable Register (VPIE)
38
Video Port Interrupt Enable Register (VPIE) Field Descriptions
38
Video Port Interrupt Status Register (VPIS)
40
Video Port Interrupt Status Register (VPIS) Field Descriptions
40
Video Capture Port
45
Video Capture Mode Selection
46
BT.656 Video Capture Mode
46
BT.656 Capture Channels
46
BT.656 Timing Reference Codes
46
BT.656 Video Timing Reference Codes
47
BT.656 Protection Bits
47
Error Correction by Protection Bits
47
BT.656 Image Window and Capture
48
Video Capture Parameters
48
BT.656 Data Sampling
49
BT.656 FIFO Packing
49
Common Video Source Parameters
49
Y/C Video Capture Mode
50
Y/C Capture Channels
50
Y/C Timing Reference Codes
50
Y/C Image Window and Capture
50
Bit BT.656 FIFO Packing
50
Y/C FIFO Packing
51
BT.656 and Y/C Mode Field and Frame Operation
51
Bit Y/C FIFO Packing
51
Capture Determination and Notification
52
BT.656 and Y/C Mode Capture Operation
52
Vertical Synchronization
53
3.3 Y/C
50
3.4 Bt.656
52
Vertical Synchronization Programming
53
VCOUNT Operation Example (EXC = 0)
54
Horizontal Synchronization
55
HCOUNT Operation Example (EXC = 0)
55
Horizontal Synchronization Programming
55
Field Identification
56
HCOUNT Operation Example (EXC = 1)
56
Field Identification Programming
56
Short and Long Field Detect
57
Video Input Filtering
57
Field 1 Detection Timing
57
Input Filter Modes
58
Chrominance Re-Sampling Operation
58
Scaling Operation
58
Chrominance Re-Sampling
58
Input Filter Mode Selection
58
Edge Pixel Replication
59
Scaled Co-Sited Filtering
59
Scaled Chrominance Re-Sampled Filtering
59
Ancillary Data Capture
60
Edge Pixel Replication
60
Capture Window Not Requiring Edge Pixel Replication
60
Horizontal Ancillary (HANC) Data Capture
61
Vertical Ancillary (VANC) Data Capture
61
Raw Data Capture Mode
61
Raw Data Capture Notification
61
Raw Data FIFO Packing
62
Bit Raw Data FIFO Packing
62
Raw Data Mode Capture Operation
62
TCI Capture Mode
63
TCI Capture Features
63
TCI Data Capture
63
Bit Raw Data FIFO Packing
63
TCI Capture Error Detection
64
Synchronizing the System Clock
64
Parallel TCI Capture
64
Program Clock Reference (PCR) Header Format
64
TCI Data Capture Notification
65
System Time Clock Counter Operation
65
TCI Capture Mode Operation
65
Writing to the FIFO
66
Reading from the FIFO
66
TCI FIFO Packing
66
TCI Timestamp Format (Little Endian)
66
Capture Line Boundary Conditions
67
Capturing Video in BT.656 or Y/C Mode
67
Capture Line Boundary Example
67
Handling FIFO Overrun in BT.656 or Y/C Mode
68
Capturing Video in Raw Data Mode
68
Handling FIFO Overrun Condition in Raw Data Mode
69
Capturing Data in TCI Capture Mode
69
Handling FIFO Overrun Condition in TCI Capture Mode
70
Video Capture Registers
70
Video Capture Control Registers
70
Video Capture Channel X Status Register (VCASTAT, VCBSTAT)
71
Video Capture Channel X Status Register (Vcxstat)
71
Video Capture Channel a Control Register (VCACTL)
72
Video Capture Channel X Status Register (Vcxstat) Field Descriptions
72
Video Capture Channel a Control Register (VCACTL)
73
Video Capture Channel a Control Register (VCACTL) Field Descriptions
73
Video Capture Channel X Field 1 Start Register (Vcxstrt1)
75
Video Capture Channel X Field 1 Stop Register (Vcxstop1)
76
Video Capture Channel X Field 1 Start Register (Vcxstrt1)
76
Video Capture Channel X Field 1 Start Register (Vcxstrt1) Field Descriptions
76
Video Capture Channel X Field 2 Start Register (Vcxstrt2)
77
Video Capture Channel X Field 1 Stop Register (Vcxstop1)
77
Video Capture Channel X Field 1 Stop Register (Vcxstop1) Field Descriptions
77
Video Capture Channel X Field 2 Stop Register (Vcxstop2)
78
Video Capture Channel X Field 2 Start Register (Vcxstrt2) Field Descriptions
78
Video Capture Channel X Field 2 Stop Register (Vcxstop2) Field Descriptions
78
Video Capture Channel X Vertical Interrupt Register (Vcxvint)
79
Video Capture Channel X Vertical Interrupt Register (Vcxvint) Field Descriptions
79
Video Capture Channel X Threshold Register (VCATHRLD, VCBTHRLD)
80
Video Capture Channel X Threshold Register (Vcxthrld)
80
Video Capture Channel X Threshold Register (Vcxthrld) Field Descriptions
80
Video Capture Channel X Event Count Register (Vcxevtct)
81
Video Capture Channel B Control Register (VCBCTL)
81
Video Capture Channel X Event Count Register (Vcxevtct) Field Descriptions
81
Video Capture Channel B Control Register (VCBCTL)
82
Video Capture Channel B Control Register (VCBCTL) Field Descriptions
82
TCI Capture Control Register (TCICTL)
84
TCI Capture Control Register (TCICTL) Field Descriptions
84
TCI Clock Initialization LSB Register (TCICLKINITL)
85
TCI Clock Initialization LSB Register (TCICLKINITL) Field Descriptions
85
TCI Clock Initialization MSB Register (TCICLKINITM)
86
TCI System Time Clock LSB Register (TCISTCLKL)
86
TCI Clock Initialization MSB Register (TCICLKINITM) Field Descriptions
86
TCI System Time Clock MSB Register (TCISTCLKM)
87
TCI System Time Clock LSB Register (TCISTCLKL)
87
TCI System Time Clock LSB Register (TCISTCLKL) Field Descriptions
87
TCI System Time Clock MSB Register (TCISTCLKM) Field Descriptions
87
TCI System Time Clock Compare LSB Register (TCISTCMPL)
88
TCI System Time Clock Compare MSB Register (TCISTCMPM)
88
TCI System Time Clock Compare LSB Register (TCISTCMPL) Field Descriptions
88
TCI System Time Clock Compare Mask LSB Register (TCISTMSKL)
89
TCI System Time Clock Compare Mask MSB Register (TCISTMSKM)
89
TCI System Time Clock Compare MSB Register (TCISTCMPM) Field Descriptions
89
TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) Field Descriptions
89
TCI System Time Clock Ticks Interrupt Register (TCITICKS)
90
TCI System Time Clock Compare Mask MSB Register (TCISTMSKM)
90
TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) Field Descriptions
90
TCI System Time Clock Ticks Interrupt Register (TCITICKS) Field Descriptions
90
Video Capture FIFO Registers
91
Video Capture FIFO Registers Function
91
Video Display Port
92
Video Display Mode Selection
93
Image Timing
93
NTSC Compatible Interlaced Display
93
SMPTE 296M Compatible Progressive Scan Display
94
Interlaced Blanking Intervals and Video Areas
95
Video Display Counters
96
Progressive Blanking Intervals and Video Area
96
Horizontal Blanking and Horizontal Sync Timing
97
Vertical Blanking, Sync and Even/Odd Frame Signal Timing
97
Sync Signal Generation
98
External Sync Operation
98
Port Sync Operation
98
BT.656 Video Display Mode
98
Video Display Module Synchronization Chain
98
BT.656 Output Sequence
98
Display Timing Reference Codes
99
BT.656 Horizontal Blanking Timing
99
4.2 Bt.656
99
Digital Vertical F and V Transitions
100
BT.656 Frame Timing
100
Blanking Codes
101
BT.656 Image Display
101
BT.656 FIFO Unpacking
101
Bit BT.656 FIFO Unpacking
101
Y/C Video Display Mode
102
Y/C Display Timing Reference Codes
102
Y/C Blanking Codes
102
Y/C Image Display
102
Y/C Horizontal Blanking Timing (BT.1120 60I)
102
Y/C FIFO Unpacking
103
Video Output Filtering
103
Output Filter Modes
103
Output Filter Mode Selection
103
Chrominance Re-Sampling Operation
104
Scaling Operation
104
X Co-Sited Scaling
104
Edge Pixel Replication
105
X Interspersed Scaling
105
Output Edge Pixel Replication
105
Luma Edge Replication
105
Ancillary Data Display
106
Horizontal Ancillary (HANC) Data Display
106
Vertical Ancillary (VANC) Data Display
106
Raw Data Display Mode
106
Interspersed Chroma Edge Replication
106
Raw Mode RGB Output Support
107
Raw Data FIFO Unpacking
107
Bit Raw FIFO Unpacking
107
Video Display Field and Frame Operation
108
Display Determination and Notification
108
Display Operation
108
Video Display Event Generation
109
Display Line Boundary Conditions
109
Display Timing Examples
110
Interlaced BT.656 Timing Example
110
Display Line Boundary Example
110
BT.656 Interlaced Display Horizontal Timing Example
111
Interlaced Raw Display Example
113
BT.656 Interlaced Display Vertical Timing Example
113
Raw Interlaced Display Horizontal Timing Example
114
Raw Interlaced Display Vertical Timing Example
115
Y/C Progressive Display Example
116
Y/C Progressive Display Horizontal Timing Example
117
Y/C Progressive Display Vertical Timing Example
118
Displaying Video in BT.656 or Y/C Mode
119
Displaying Video in Raw Data Mode
120
4.11 Displaying
121
4.10 Displaying
121
Handling Under-Run Condition of the Display FIFO
121
Video Display Registers
122
Video Display Status Register (VDSTAT)
122
Video Display Control Registers
122
Video Display Control Register (VDCTL)
123
Video Display Status Register (VDSTAT)
123
Video Display Status Register (VDSTAT) Field Descriptions
123
Video Display Control Register (VDCTL)
124
Video Display Control Register (VDCTL) Field Descriptions
124
Video Display Frame Size Register (VDFRMSZ)
127
Video Display Horizontal Blanking Register (VDHBLNK)
127
Video Display Frame Size Register (VDFRMSZ) Field Descriptions
127
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
128
Video Display Horizontal Blanking Register (VDHBLNK)
128
Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions
128
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
129
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
129
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) Field Descriptions
129
Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
130
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions
130
Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions
130
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
131
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) Field Descriptions
131
Video Display Field 1 Image Offset Register (VDIMGOFF1)
132
Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions
132
Video Display Field 1 Image Size Register (VDIMGSZ1)
133
Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions
133
Video Display Field 2 Image Offset Register (VDIMGOFF2)
134
Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions
134
Video Display Field 2 Image Size Register (VDIMGSZ2)
135
Video Display Field 1 Timing Register (VDFLDT1)
135
Video Display Field 2 Image Size Register (VDIMGSZ2) Field Descriptions
135
Video Display Field 2 Timing Register (VDFLDT2)
136
Video Display Field 1 Timing Register (VDFLDT1)
136
Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions
136
Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions
136
Video Display Threshold Register (VDTHRLD)
137
Video Display Threshold Register (VDTHRLD) Field Descriptions
137
Video Display Horizontal Synchronization Register (VDHSYNC)
138
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)
138
Video Display Horizontal Synchronization Register (VDHSYNC) Field Descriptions
138
Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
139
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)
139
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) Field Descriptions
139
Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Field Descriptions
139
Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
140
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
140
Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) Field Descriptions
140
Video Display Counter Reload Register (VDRELOAD)
141
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
141
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) Field Descriptions
141
Video Display Counter Reload Register (VDRELOAD) Field Descriptions
141
Video Display Event Register (VDDISPEVT)
142
Video Display Clipping Register (VDCLIP)
142
Video Display Event Register (VDDISPEVT) Field Descriptions
142
Video Display Default Display Value Register (VDDEFVAL)
143
Video Display Clipping Register (VDCLIP)
143
Video Display Clipping Register (VDCLIP) Field Descriptions
143
Video Display Vertical Interrupt Register (VDVINT)
144
Video Display Default Display Value Register (VDDEFVAL)
144
Video Display Default Display Value Register (VDDEFVAL) - Raw Data Mode
144
Video Display Default Display Value Register (VDDEFVAL) Field Descriptions
144
Video Display Field Bit Register (VDFBIT)
145
Video Display Vertical Interrupt Register (VDVINT)
145
Video Display Vertical Interrupt Register (VDVINT) Field Descriptions
145
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)
146
Video Display Field Bit Register (VDFBIT)
146
Video Display Field Bit Register (VDFBIT) Field Descriptions
146
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)
147
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions
147
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions
147
Video Display Registers Recommended Values
148
Video Display Register Recommended Values
148
Video Display FIFO Registers
149
Video Display FIFO Registers Function
149
General-Purpose I/O Operation
150
GPIO Registers
151
Video Port Registers
151
Video Port Peripheral Identification Register (VPPID)
152
Video Port Peripheral Identification Register (VPPID) Field Descriptions
152
Video Port Peripheral Control Register (PCR)
153
Video Port Peripheral Control Register (PCR) Field Descriptions
153
Video Port Pin Function Register (PFUNC)
154
Video Port Pin Function Register (PFUNC) Field Descriptions
154
Video Port Pin Direction Register (PDIR)
156
Video Port Pin Direction Register (PDIR) Field Descriptions
156
Video Port Pin Data Input Register (PDIN)
158
Video Port Pin Data Input Register (PDIN) Field Descriptions
158
Video Port Pin Data Output Register (PDOUT)
159
Video Port Pin Data out Register (PDOUT) Field Descriptions
159
Video Port Pin Data Set Register (PDSET)
161
Video Port Pin Data Set Register (PDSET) Field Descriptions
161
Video Port Pin Data Clear Register (PDCLR)
162
Video Port Pin Data Clear Register (PDCLR) Field Descriptions
162
Video Port Pin Interrupt Enable Register (PIEN)
163
Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions
163
Video Port Pin Interrupt Polarity Register (PIPOL)
164
Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions
164
Video Port Pin Interrupt Status Register (PISTAT)
165
Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions
165
Video Port Pin Interrupt Clear Register (PICLR)
166
Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions
166
VCXO Interpolated Control Port
167
6 Vcxo
168
Overview
168
Interface
168
TCI System Block Diagram
168
VIC Port Interface Signals
168
Operational Details
169
Program Clock Reference (PCR) Header Format
169
Example Values for Interpolation Rate
169
Enabling VIC Port
170
VIC Port Registers
170
VIC Clock Divider Register (VICDIV
170
VIC Control Register (VICCTL
170
VIC Input Register (VICIN
170
VIC Control Register (VICCTL)
171
VIC Control Register (VICCTL) Field Descriptions
171
VIC Input Register (VICIN)
172
VIC Input Register (VICIN) Field Descriptions
172
VIC Clock Divider Register (VICDIV)
173
VIC Clock Divider Register (VICDIV) Field Descriptions
173
Important Notice
174
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Texas Instruments TMS320DM647 User Manual (47 pages)
DSP DDR2 Memory Controller
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.42 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
9
Industry Standard(S) Compliance Statement
10
DDR2 Memory Controller Block Diagram
10
Peripheral Architecture
11
Clock Control
11
Memory Map
11
Signal Descriptions
11
DDR2 Memory Controller Signals
12
DDR2 Memory Controller Signal Descriptions
12
Protocol Description(S)
13
DDR2 SDRAM Commands
13
Truth Table for DDR2 SDRAM Commands
13
DDR2 MRS and EMRS Command
14
Refresh Command
15
ACTV Command
15
DCAB Command
16
DEAC Command
16
DDR2 READ Command
17
Memory Width and Byte Alignment
18
DDR2 WRT Command
18
Addressable Memory Ranges
18
Address Mapping
19
Byte Alignment
19
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
19
Bank Configuration Register Fields for Address Mapping
19
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
20
Logical Address-To-DDR2 SDRAM Address Map
21
DDR2 Memory Controller Interface
22
DDR2 SDRAM Column, Row, and Bank Access
22
DDR2 Memory Controller FIFO Description
22
DDR2 Memory Controller FIFO Block Diagram
23
Refresh Scheduling
25
Refresh Urgency Levels
25
Self-Refresh Mode
26
2.10 Reset Considerations
26
DDR2 Memory Controller Reset Block Diagram
26
Reset Sources
26
2.11 DDR2 SDRAM Memory Initialization
27
DDR2 SDRAM Mode Register Configuration
27
DDR2 SDRAM Extended Mode Register 1 Configuration
27
2.12 Interrupt Support
28
2.13 EDMA Event Support
28
2.14 Emulation Considerations
28
Using the DDR2 Memory Controller
29
Connecting the DDR2 Memory Controller to DDR2 SDRAM
29
Connecting to Two 16-Bit DDR2 SDRAM Devices
30
Connecting to a Single 16-Bit DDR2 SDRAM Device
31
Connecting to Two 8-Bit DDR2 SDRAM Devices
32
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
33
SDCFG Configuration
33
DDR2 Memory Refresh Specification
34
SDRFC Configuration
34
SDTIM1 Configuration
34
SDTIM2 Configuration
35
DMCCTL Configuration
35
DDR2 Memory Controller Registers
36
Module ID and Revision Register (MIDR)
37
DDR2 Memory Controller Status Register (DMCSTAT)
37
Module ID and Revision Register (MIDR) Field Descriptions
37
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
37
SDRAM Configuration Register (SDCFG)
38
SDRAM Configuration Register (SDCFG) Field Descriptions
38
SDRAM Refresh Control Register (SDRFC)
40
SDRAM Refresh Control Register (SDRFC) Field Descriptions
40
SDRAM Timing 1 Register (SDTIM1)
41
SDRAM Timing 1 Register (SDTIM1) Field Descriptions
41
SDRAM Timing 2 Register (SDTIM2)
43
SDRAM Timing 2 Register (SDTIM2) Field Descriptions
43
Burst Priority Register (BPRIO)
44
Burst Priority Register (BPRIO) Field Descriptions
44
DDR2 Memory Controller Control Register (DMCCTL)
45
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
45
Appendix A Revision History
46
Document Revision History
46
Important Notice
47
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