Table of Contents
Advertisement
www.ti.com
5.1.11 Video Port Pin Interrupt Status Register (PISTAT)
PISTAT is a read-only register that indicates the GPIO pin that has a pending interrupt.
A bit in PISTAT is set when the corresponding GPIO pin is configured as an interrupt (the corresponding
bit in PIEN is set, the pin is enabled for GPIO in PFUNC, and the pin is configured as an input in PDIR)
and the appropriate transition (as selected by the corresponding PIPOL bit) occurs on the pin. Whenever a
PISTAT bit is set to 1, the GPIO bit in VPIS is set. The PISTAT bits are cleared by writing a 1 to the
corresponding bit in PICLR. Writing a 0 has no effect. Clearing all the PISTAT bits does not clear the
GPIO bit in VPIS, it must be explicitly cleared. If any bits in PISTAT are still set when the GPIO bit is
cleared, the GPIO bit is set again.
The video port pin interrupt status register (PISTAT) is shown in
31
23
22
Reserved
PISTAT22
R-0
R-0
15
14
PISTAT15
PISTAT14
R-0
R-0
7
6
PISTAT7
PISTAT6
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-12. Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PISTAT22
OF(value)
DEFAULT
NONE
VCTL3INT
21
PISTAT21
OF(value)
DEFAULT
NONE
VCTL2INT
20
PISTAT20
OF(value)
DEFAULT
NONE
VCTL1INT
19-2
PISTAT[19-2]
OF(value)
DEFAULT
NONE
VDATAnINT
(1)
For CSL implementation, use the notation VP_PISTAT_PISTATn_symval
SPRUEM1 – May 2007
Submit Documentation Feedback
Figure 5-11. Video Port Pin Interrupt Status Register (PISTAT)
21
20
PISTAT21
PISTAT20
R-0
R-0
13
12
PISTAT13
PISTAT12
R-0
R-0
5
4
PISTAT5
PISTAT4
R-0
R-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
PISTAT22 bit indicates if there is a pending interrupt on the VCTL3 pin.
0
No pending interrupt on the VCTL3 pin.
1
Pending interrupt on the VCTL3 pin.
PISTAT21 bit indicates if there is a pending interrupt on the VCTL2 pin.
0
No pending interrupt on the VCTL2 pin.
1
Pending interrupt on the VCTL2 pin.
PISTAT20 bit indicates if there is a pending interrupt on the VCTL1 pin.
0
No pending interrupt on the VCTL1 pin.
1
Pending interrupt on the VCTL1 pin.
PISTAT[19-2] bit indicates if there is a pending interrupt on the corresponding
VDATA[n] pin.
0
No pending interrupt on the VDATA[n] pin.
1
Pending interrupt on the VDATA[n] pin.
Figure 5-11
Reserved
R-0
19
18
PISTAT19
PISTAT18
R-0
R-0
11
10
Reserved
Reserved
R-0
R-0
3
2
PISTAT3
PISTAT2
R-0
R-0
GPIO Registers
and described in
Table
24
17
16
PISTAT17
PISTAT16
R-0
R-0
9
8
PISTAT9
PISTAT8
R-0
R-0
1
0
Reserved
Reserved
R-0
R-0
General-Purpose I/O Operation
5-12.
165
Advertisement
Table of Contents
