10/100/1000 Tri-Speed Ethernet Phy - Xilinx VC707 User Manual

Table 1-15
Table 1-15: FPGA U1 GTX Bank 113 to SFP+ Module Connections
Table 1-16
Table 1-16: SFP+ Module Control and Status
SFP_TX_FAULT
SFP_TX_DISABLE
SFP_MOD_DETECT
SFP_RS0
SFP_RS1
SFP_LOS

10/100/1000 Tri-Speed Ethernet PHY

[Figure
The VC707 board utilizes the Marvell Alaska PHY device (88E1111) U50 for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports SGMII mode only. The PHY
connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P4)
with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY address
0b00111 using the settings shown in
commands passed over the MDIO interface.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
lists the SFP+ module RX and TX connections to the FPGA.
FPGA (U1) Pin Schematic Net Name
AL5
AL6
AM4
AM3
AP33 SFP_TX_DISABLE_TRANS
lists the SFP+ module control and status connections to the FPGA.
SFP Control/Status
Signal
Test Point J22
Jumper J6
Test Point J21
Jumper J38
Jumper J39
Test Point J20
1-2, callout 15]
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SFP_RX_N
SFP_RX_P
SFP_TX_P
SFP_TX_N
Board Connection
High = Fault
Low = Normal Operation
Off = SFP Disabled
On = SFP Enabled
High = Module Not Present
Low = Module Present
Jumper Pins 1-2 = Full RX Bandwidth
Jumper Pins 2-3 = Reduced RX Bandwidth
Jumper Pins 1-2 = Full TX Bandwidth
Jumper Pins 2-3 = Reduced TX Bandwidth
High = Loss of Receiver Signal
Low = Normal Operation
Table 1-17. These settings can be overwritten by software
Feature Descriptions
SFP+ Module (P3)
Pin Name
12 RD_N
13 RD_P
18 TD_P
19 TD_N
3 TX_DISABLE
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