10/100/1000 Mhz Tri-Speed Ethernet Phy - Xilinx ZC702 User Manual

For more details, see the SiTime SiT8103 data sheet
The system clock circuit is shown in
X-Ref Target - Figure 1-13

10/100/1000 MHz Tri-Speed Ethernet PHY

[Figure 1-2, callout 9]
The ZC702 board uses the Marvell Alaska PHY device (88E1116R) at U35 for Ethernet
communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports RGMII mode
only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E
RJ-45 connector (P2) with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in RGMII mode with PHY
address
0b00111
using software commands passed over the MDIO interface.
Table 1-13: Board Connections for PHY Configuration Pins
U35 Pin
CONFIG0
CONFIG1
CONFIG2
CONFIG3
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Figure
U65
VCC1V8
SiT8103
MEMS Clock
R322
Oscillator
4.7KΩ 5%
33.33333 MHz
1
OE
2
GND
GND
Figure 1-13: Processing System Clock Source
using the settings shown in
Setting Configuration
VCCO_MIO1 PHYAD[1]=1
EPHY_LED0 PHYAD[3]=0
GND ENA_XC=0
EPHY_LED0 ENA_XC=0
VCCO_MIO1 ENA_XC=1
GND RGMII_TX=0
EPHY_LED0 RGMII_TX=0
EPHY_LED1 RGMII_TX=1
VCCO_MIO1 RGMII_TX=1
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[Ref 18].
1-13.
VCC1V8
C449
0.01 μF 25V
X7R
4
VDD GND
R403
24.9Ω 1%
3
OUT
UG850_c1_13_030513
Table 1-13. These settings can be overwritten
PHYAD[0]=1
PHYAD[2]=1
PHYAD[4]=0
PHYAD[4]=1
PHYAD[4]=1
RGMII_RX=0
RGMII_RX=1
RGMII_RX=0
RGMII_RX=1
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