10/100/1000 Tri-Speed Ethernet Phy - Xilinx KC705 User Manual

Chapter 1: KC705 Evaluation Board Features
Table 1-14: FPGA U1 to SFP+ Module Connections (Cont'd)
Notes:
1. On KC705 boards prior to Rev 1.1, SFP+ connector P5 pin 18 TD_P is connected to net
Table 1-15
Table 1-15: SFP+ Module Control and Status

10/100/1000 Tri-Speed Ethernet PHY

[Figure
The KC705 board utilizes the Marvell Alaska PHY device (88E1111) U37 for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and
SGMII interfaces from the FPGA to the PHY
user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P3) with
built-in magnetics.
36
FPGA Pin Schematic
(U1) Net Name
Y20 SFP_TX_DISABLE_TRANS
SFP_TX_N, and pin 19 TD_N is connected to net SFP_TX_P.
lists the SFP+ module control and status connections to the FPGA.
SFP Control/Status
Signal
SFP_TX_FAULT Test Point J10
High = Fault
Low = Normal Operation
SFP_TX_DISABLE Jumper J4
Off = FP Disabled
On = SFP Enabled
SFP_MOD_DETECT Test Point J9
High = Module Not Present
Low = Module Present
SFP_RS0 Jumper J27
Jumper Pins 1-2 = Full RX Bandwidth
Jumper Pins 2-3 = Reduced RX Bandwidth
SFP_RS1 Jumper J28
Jumper Pins 1-2 = Full TX Bandwidth
Jumper Pins 2-3 = Reduced TX Bandwidth
SFP_LOS Test Point J8
High = Loss of Receiver Signal
Low = Normal Operation
1-2, callout 15]
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SFP+ Pin SFP+ Pin Name
(P5)
3
Board Connection
(Table 1-16). The PHY connection to a
(P5)
TX_DISABLE
KC705 Evaluation Board
UG810 (v1.3) May 10, 2013