100/1000 Tri-Speed Ethernet Phy - Xilinx ML405 User Manual

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21. 10/100/1000 Tri-Speed Ethernet PHY

The ML405 evaluation platform contains a Marvell Alaska PHY device (88E1111) operating
at 10/100/1000 Mb/s
interface modes with the FPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 (or
compatible) connector with built-in magnetics. A 25-MHz crystal supplies the clock signal
to the PHY. The PHY is configured to default at power-on or reset to the settings shown in
Table 1-19, page
Table 1-13: Board Connections for PHY Configuration Pins
Connection on
Config Pin
Board
CONFIG0 VCC 2.5V
CONFIG1 Ground
CONFIG2 VCC 2.5V
CONFIG3 VCC 2.5V
CONFIG4 VCC 2.5V
CONFIG5 VCC 2.5V
CONFIG6 LED_RX
Jumpers J48, J49, and J57 allow the user to select the default interface that the PHY uses
(Table
Table 1-14: PHY Default Interface Mode
ML405 Evaluation Platform
UG210 (v1.5.1) March 10, 2008
(Table
31. These settings can be overwritten via software, except PHYADR[4:0].
Bit[2] Definition and
Value
PHYADR[2] = 1
ENA_PAUSE = 0
ANEG[3] = 1
ANEG[0] = 1
HWCFG_MODE[2] = 1
DIS_FC = 1
SEL_BDT = 0
1-14). The interface can also be changed via MDIO commands.
Mode
GMII/MII
to copper Jumper over pins 1-2
(default)
SGMII to copper,
Jumper over pins 2-3
no clock
RGMII Jumper over pins 1-2
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1-13). The board supports MII, GMII, RGMII, and SGMII
Bit[1] Definition and
Value
PHYADR[1] = 1
PHYADR[4] = 0
ANEG[2] = 1
ENA_XC = 1
HWCFG_MODE[1] = 1
DIS_SLEEP = 1
INT_POL = 1
Jumper Settings
J48 J49
Jumper over pins 1-2
Jumper over pins 2-3
No jumper
Detailed Description
Bit[0] Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MODE[0] = 1
HWCFG_MODE[3] = 1
75/50Ω = 0
J57
No jumper
No jumper
Jumper on
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